ARM60
Data Sheet
Zarlink Part Number: P60ARM-B/IG/GP1N
Notes
1)
2)
The original P60ARM/CG/GPFR is obsolete
This datasheet includes the performance data previously supplied in supplement
MS4396 - Jan 1996
Preface
The ARM60 is a low power, general purpose 32-bit RISC microprocessor. It is an implementation of the
ARM6 macrocell, packaged in a 100 pin Metric Quad Flat Pack. Its simple, elegant and fully static design is
particularly suitable for cost and power sensitive applications .
t
32 bit RISC processor
Address Register
t
32 bit data bus
t
32 bit address bus
Address
Incrementer
Instruction
Decoder
&
Logic
Control
t
Big and Little Endian operating modes
t
High performance RISC
21 MIPS sustained @ 30MHz (30 MIPS peak) @ 5V
t
Low power consumption
1.5mA/MHz @ 5V fabricated in 1µm CMOS
t
Fully static operation
ideal for power sensitive applications
t
Fast interrupt response
for real-time applications
t
Virtual Memory System Support
t
Excellent high-level language support
t
Simple but powerful instruction set
t
IEEE 1149.1 (JTAG) Boundary Scan
to ease testing
Register Bank
Booth’s
Multiplier
Barrel
Shifter
32 bit ALU
Instruction
Pipeline &
Read Data
Register
Write Data Register
Applications:
The ARM60 is ideally suited to those applications requiring RISC performance from a compact, power
efficient processor. These include:
Telecomms
- eg GSM terminal controller
Datacomms
- eg protocol conversion
Portable Computing
- eg palmtop computer
Portable Instruments
- eg handheld data acquisition unit
Automotive
- eg engine management unit
Consumer Multimedia
- low cost controller
Preface-ii
Table of Contents
1.0
Introduction
1.1
1.2
ARM60 Block diagram
ARM60 Functional Diagram
1
2
3
2.0
3.0
Signal Description
Programmer's Model
3.1
3.2
3.3
3.4
3.5
Hardware Configuration
Operating Mode Selection
Registers
Exceptions
Reset
Instruction Set Summary
The Condition Field
Branch and Branch with link (B, BL)
Data processing
PSR Transfer (MRS, MSR)
Multiply and Multiply-Accumulate (MUL, MLA)
Single data transfer (LDR, STR)
Block data transfer (LDM, STM)
Single data swap (SWP)
Software interrupt (SWI)
Coprocessor data operations (CDP)
Coprocessor data transfers (LDC, STC)
Coprocessor register transfers (MRC, MCR)
Undefined instruction
Instruction Set Examples
Cycle types
Byte addressing
Address timing
Memory management
Locked operations
Stretching access times
Interface signals
Data transfer cycles
Register transfer cycle
Privileged instructions
Idempotency
Undefined instructions
Branch and branch with link
Data Operations
Multiply and multiply accumulate
Load register
Store register
5
9
9
9
10
13
17
4.0
Instruction Set
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
19
19
20
21
23
30
34
36
41
48
50
52
54
57
59
60
5.0
Memory Interface
5.1
5.2
5.3
5.4
5.5
5.6
65
65
66
68
68
69
69
6.0
Coprocessor Interface
6.1
6.2
6.3
6.4
6.5
6.6
71
71
72
72
72
72
73
7.0
Instruction Cycle Operations
7.1
7.2
7.3
7.4
7.5
75
75
75
77
77
78
iii
P60ARM-B
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
Load multiple registers
Store multiple registers
Data swap
Software interrupt and exception entry
Coprocessor data operation
Coprocessor data transfer (from memory to coprocessor)
Coprocessor data transfer (from coprocessor to memory)
Coprocessor register transfer (Load from coprocessor)
Coprocessor register transfer (Store to coprocessor)
Undefined instructions and coprocessor absent
Unexecuted instructions
Instruction Speed Summary
Overview
Reset
Pullup Resistors
Instruction Register
Public Instructions
Test Data Registers
Boundary Scan Interface Signals
Absolute Maximum Ratings
DC Operating Conditions
Notes on AC Parameters
79
81
81
82
83
83
85
86
86
87
87
88
8.0
Boundary Scan Test Interface
8.1
8.2
8.3
8.4
8.5
8.6
8.7
89
89
90
90
90
90
94
97
9.0
DC Parameters
9.1
9.2
101
101
101
10.0
11.0
12.0
13.0
AC Parameters
10.1
105
112
Physical Details
Pinout
Appendix - Backward Compatibility
113
115
117
iv
Introduction
1.0 Introduction
The ARM60 is part of the Advanced RISC Machines (ARM) family of general purpose 32-bit
microprocessors, which offer very low power consumption and price for high performance devices. The
architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and
related decode mechanism are much simpler in comparison with microprogrammed Complex Instruction
Set Computers. This results in a high instruction throughput and impressive real-time interrupt response
from a small and cost-effective chip.
The instruction set comprises eleven basic instruction types:
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Two of these make use of the on-chip arithmetic logic unit, barrel shifter and multiplier to perform
high-speed operations on the data in a bank of 31 registers, each 32 bits wide;
Three classes of instruction control data transfer between memory and the registers, one optimised
for flexibility of addressing, another for rapid context switching and the third for swapping data;
Three instructions control the flow and privilege level of execution; and
Three types are dedicated to the control of external coprocessors which allow the functionality of
the instruction set to be extended off-chip in an open and uniform way.
The ARM instruction set is a good target for compilers of many different high-level languages. Where
required for critical code segments, assembly code programming is also straightforward, unlike some RISC
processors which depend on sophisticated compiler technology to manage complicated instruction
interdependencies.
Pipelining is employed so that all parts of the processing and memory systems can operate continuously.
Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is
being fetched from memory.
The memory interface has been designed to allow the performance potential to be realised without
incurring high costs in the memory system. Speed critical control signals are pipelined to allow system
control functions to be implemented in standard low-power logic, and these control signals facilitate the
exploitation of the fast access modes offered by industry standard dynamic RAMs.
ARM60 has a 32 bit address bus. All ARM processors share the same instruction set, and ARM60 can be
configured to use a 26 bit address bus for backwards compatibility with earlier processors.
ARM60 is a fully static CMOS implementation of the ARM which allows the clock to be stopped in any part
of the cycle with extremely low residual power consumption and no loss of state.
Notation:
0x
BOLD
binary
- marks a Hexadecimal quantity
- external signals are shown in bold capital letters
- where it is not clear that a quantity is binary it is followed by the word binary
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