VCPL
(VCXO)
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HIGH-FREQUENCY VCXO IN THRU-HOLE OR SMD METAL PACKAGE
PHASED-LOCK LOOP CIRCUIT (PLLC) USED
300 pS RMS MAXIMUM JITTER
STANDARD SPECIFICATIONS:
Frequency Range
Operating Temperature Range
Frequency Stability over Operating
Temperature Range and Supply Voltage
Aging
Input Voltage
Output Logic Level
Input Current (Icc) & Rise & Fall Time (Tr & Tf)
Output Load
Control Voltage Range
Frequency Deviation (Pullability) over the
Control Voltage Range
Linearity
Packaging
60.000 - 160.000 MHz
(Consult factory for specific available frequencies)
0 - 70°C is standard, but can be extended to
−
40 to +85°C
±
100 PPM is standard but
±
15, 25, 50 ppm also available.
3 PPM first year, 1 PPM per year thereafter at 25°C
±
5°C
5 V
±
5% Volt is standard but 3.3 V± 5% also available
HCMOS/TTL Compatible
Depends on frequency. See table on next page.
CMOS Load + 15 pF
2.5V
±
2.0V for Vcc = 5.0V, 1.65V
±
1.32V for Vcc = 3.3V
±
25, 50, 100, 150, 200, and 300 PPM available.
±
10%
20 parts per tube, SMD: Tape and Reel TBD
PART NUMBERING GUIDE:
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The Pletronics part number for a VCPL VCXO consists of the following 6 elements:
1.
Model Number (Voltage):
VCPL = 5V
3VCPL = 3.3V
2.
Frequency Stability:
VCPL15:
±15
PPM
VCPL25:
±25
PPM
VCPL50:
±50
PPM
VCPL100:
±100
PPM
3.
Operating Temperature Range:
VCPL100A: 0 to +50°
VCPL100C: -10 to +70°C
VCPL100E: -30 to +75°C
VCPL100B: 0 to +70°C
VCPL100D:-20 to +75°C
VCPL100F:-40 to +85°C
4.
Frequency Deviation over Control Voltage Range:
VCPL100AT:
±25
PPM
VCPL100AV:
±50
PPM
VCPL100AW:
±100
PPM
VCPL100AX:
±150
PPM
VCPL100AY:
±200
PPM
VCPL100AZ:
±300
PPM
Frequency of Operation in MHz
Optional Surface Mount Configuration - SMD
5.
6.
EXAMPLE: VCPL100CW-60.000 MHz, VCPL50DZ-60.000 MHz-SMD, 3VCPL15FT-60.000 MHz
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When customer’s requirements are non-standard, a special engineering part number will be assigned.
(continued)
Telephone: (425) 776-1880, Fax: (425) 776-2760, e-mail: ple-sales@pletronics.com
T3A
VCPL VCXO
Input Current and Rise & Fall Time with 15 pF CMOS Load
Freq. Range
(MHz)
60.000 – 100.000
100.001 – 120.000
120.001 – 140.000
140.001 – 160.000
Icc (mA)
Typ
25.0
30.0
35.0
40.0
Max
30.0
35.0
40.0
45.0
Tr & Tf (nS)
Typ
1.5
1.5
1.5
1.5
Max
2.5
2.5
2.5
2.5
Recommended Test Circuit
*
*CL (Capacitive Load): Includes the
input capacitance of oscilloscope
Package Outline (Not to Scale):
PIN CONNECTIONS
PIN
1
7
8
14
CONNECTION
Vcontrol
GROUND & CASE
OUTPUT
Vcc
SMD OUTLINE
INCHES (MILLIMETERS)
January 2000
T3B
Pletronics Inc., 19013 36
th
Ave. W., Suite H, Lynnwood, WA 98036-5761 USA
FPGA/CPLD
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