Typicals represent average readings at +25°C and V
DD
= +5 V, V
SS
= −5 V.
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
W
= V
DD
/R for both V
DD
= +5 V and
V
SS
= –5 V.
3
V
AB
= V
DD
, Wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
V
L
is limited to V
DD
or 5.5 V, whichever is less.
9
Worst-case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
10
P
DISS
is calculated from I
DD
× V
DD
. CMOS logic level inputs result in minimum power dissipation.
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FPGA/CPLD
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