DM74S175N datasheet, PDF - EEWORLD Datasheet

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DM74S175N: DescriptionHex/Quad D Flip-Flop with Clear; Categorylogic logic; File Size54KB，5 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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DM74S175N Overview

Hex/Quad D Flip-Flop with Clear

DM74S175N Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Fairchild
Parts packaging code	DIP
package instruction	DIP, DIP16,.3
Contacts	16
Reach Compliance Code	unknow
series	S
JESD-30 code	R-PDIP-T16
JESD-609 code	e0
length	19.305 mm
Logic integrated circuit type	D FLIP-FLOP
Maximum Frequency@Nom-Su	65000000 Hz
MaximumI(ol)	0.02 A
Number of digits	4
Number of functions	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	96 mA
propagation delay (tpd)	21 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	7.62 mm
minfmax	110 MHz

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DM74S174 • DM74S175 Hex/Quad D Flip-Flop with Clear

August 1986

Revised April 2000

DM74S174 • DM74S175

Hex/Quad D Flip-Flop with Clear

General Description

These positive-edge-triggered flip-flops utilize TTL circuitry

to implement D-type flip-flop logic. All have a direct clear

input, and the quad (DM74S175) versions feature comple-

mentary outputs from each flip-flop.

Information at the D inputs meeting the setup time require-

ments is transferred to the Q outputs on the positive-going

edge of the clock pulse. Clock triggering occurs at a partic-

ular voltage level and is not directly related to the transition

time of the positive-going pulse. When the clock input is at

either the HIGH or LOW level, the D input signal has no

effect at the output.

Features

DM74S174 contain six flip-flops with single-rail outputs.

DM74S175 contain four flip-flops with double-rail out-

puts.

Buffered clock and direct clear inputs

Individual data input to each flip-flop

Applications include:

Buffer/storage registers

Shift registers

Pattern generators

Typical clock frequency 110 MHz

Typical power dissipation per flip-flop 75mW

Ordering Code:

Order Number

DM74S174N

DM74S175N

Package Number

N16E

Package Description

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagrams

DM74S174

DM74S175

DS006472

www.fairchildsemi.com

DM74S175N Related Products

	DM74S175N	DM74S174N	DM74S174
Description	Hex/Quad D Flip-Flop with Clear	Hex/Quad D Flip-Flop with Clear	Hex/Quad D Flip-Flop with Clear
Is it Rohs certified?	incompatible	incompatible	-
Maker	Fairchild	Fairchild	-
Parts packaging code	DIP	DIP	-
package instruction	DIP, DIP16,.3	DIP, DIP16,.3	-
Contacts	16	16	-
Reach Compliance Code	unknow	unknow	-
series	S	S	-
JESD-30 code	R-PDIP-T16	R-PDIP-T16	-
JESD-609 code	e0	e0	-
length	19.305 mm	19.305 mm	-
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	-
MaximumI(ol)	0.02 A	0.02 A	-
Number of digits	4	6	-
Number of functions	1	1	-
Number of terminals	16	16	-
Maximum operating temperature	70 °C	70 °C	-
Output polarity	COMPLEMENTARY	TRUE	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	DIP	DIP	-
Encapsulate equivalent code	DIP16,.3	DIP16,.3	-
Package shape	RECTANGULAR	RECTANGULAR	-
Package form	IN-LINE	IN-LINE	-
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	-
power supply	5 V	5 V	-
Maximum supply current (ICC)	96 mA	144 mA	-
propagation delay (tpd)	21 ns	21 ns	-
Certification status	Not Qualified	Not Qualified	-
Maximum seat height	5.08 mm	5.08 mm	-
Maximum supply voltage (Vsup)	5.25 V	5.25 V	-
Minimum supply voltage (Vsup)	4.75 V	4.75 V	-
Nominal supply voltage (Vsup)	5 V	5 V	-
surface mount	NO	NO	-
technology	TTL	TTL	-
Temperature level	COMMERCIAL	COMMERCIAL	-
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
Terminal form	THROUGH-HOLE	THROUGH-HOLE	-
Terminal pitch	2.54 mm	2.54 mm	-
Terminal location	DUAL	DUAL	-
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-
Trigger type	POSITIVE EDGE	POSITIVE EDGE	-
width	7.62 mm	7.62 mm	-
minfmax	110 MHz	110 MHz	-

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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