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DM74S174N

Description
Hex/Quad D Flip-Flop with Clear
Categorylogic    logic   
File Size54KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74S174N Overview

Hex/Quad D Flip-Flop with Clear

DM74S174N Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instructionDIP, DIP16,.3
Contacts16
Reach Compliance Codeunknow
seriesS
JESD-30 codeR-PDIP-T16
JESD-609 codee0
length19.305 mm
Logic integrated circuit typeD FLIP-FLOP
MaximumI(ol)0.02 A
Number of digits6
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)144 mA
Prop。Delay @ Nom-Su21 ns
propagation delay (tpd)21 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width7.62 mm
minfmax110 MHz
DM74S174 • DM74S175 Hex/Quad D Flip-Flop with Clear
August 1986
Revised April 2000
DM74S174 • DM74S175
Hex/Quad D Flip-Flop with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (DM74S175) versions feature comple-
mentary outputs from each flip-flop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a partic-
ular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the HIGH or LOW level, the D input signal has no
effect at the output.
Features
s
DM74S174 contain six flip-flops with single-rail outputs.
s
DM74S175 contain four flip-flops with double-rail out-
puts.
s
Buffered clock and direct clear inputs
s
Individual data input to each flip-flop
s
Applications include:
Buffer/storage registers
Shift registers
Pattern generators
s
Typical clock frequency 110 MHz
s
Typical power dissipation per flip-flop 75mW
Ordering Code:
Order Number
DM74S174N
DM74S175N
Package Number
N16E
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagrams
DM74S174
DM74S175
© 2000 Fairchild Semiconductor Corporation
DS006472
www.fairchildsemi.com

DM74S174N Related Products

DM74S174N DM74S175N DM74S174
Description Hex/Quad D Flip-Flop with Clear Hex/Quad D Flip-Flop with Clear Hex/Quad D Flip-Flop with Clear
Is it Rohs certified? incompatible incompatible -
Maker Fairchild Fairchild -
Parts packaging code DIP DIP -
package instruction DIP, DIP16,.3 DIP, DIP16,.3 -
Contacts 16 16 -
Reach Compliance Code unknow unknow -
series S S -
JESD-30 code R-PDIP-T16 R-PDIP-T16 -
JESD-609 code e0 e0 -
length 19.305 mm 19.305 mm -
Logic integrated circuit type D FLIP-FLOP D FLIP-FLOP -
MaximumI(ol) 0.02 A 0.02 A -
Number of digits 6 4 -
Number of functions 1 1 -
Number of terminals 16 16 -
Maximum operating temperature 70 °C 70 °C -
Output polarity TRUE COMPLEMENTARY -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code DIP DIP -
Encapsulate equivalent code DIP16,.3 DIP16,.3 -
Package shape RECTANGULAR RECTANGULAR -
Package form IN-LINE IN-LINE -
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED -
power supply 5 V 5 V -
Maximum supply current (ICC) 144 mA 96 mA -
propagation delay (tpd) 21 ns 21 ns -
Certification status Not Qualified Not Qualified -
Maximum seat height 5.08 mm 5.08 mm -
Maximum supply voltage (Vsup) 5.25 V 5.25 V -
Minimum supply voltage (Vsup) 4.75 V 4.75 V -
Nominal supply voltage (Vsup) 5 V 5 V -
surface mount NO NO -
technology TTL TTL -
Temperature level COMMERCIAL COMMERCIAL -
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) -
Terminal form THROUGH-HOLE THROUGH-HOLE -
Terminal pitch 2.54 mm 2.54 mm -
Terminal location DUAL DUAL -
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED -
Trigger type POSITIVE EDGE POSITIVE EDGE -
width 7.62 mm 7.62 mm -
minfmax 110 MHz 110 MHz -
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