4M x 4-Bit Dynamic RAM
HYB5117400BJ -50/-60/-70
HYB5117400BT -50/-60/-70
Advanced Information
•
•
•
4 194 304 words by 4-bit organization
0 to 70 °C operating temperature
Performance:
-50
tRAC
tCAC
tAA
tRC
tPC
RAS access time
CAS access time
Access time from address
Read/Write cycle time
Fast page mode cycle time
50
13
25
90
35
-60
60
15
30
110
40
-70
70
20
35
130
45
ns
ns
ns
ns
ns
•
•
Single + 5 V (± 10 %) supply
Low power dissipation
max. 660 active mW (-50 version)
max. 605 active mW (-60 version)
max. 550 active mW (-70 version)
11 mW standby (TTL)
5.5. mW standby (MOS)
Output unlatched at cycle end allows two-dimensional chip selection
Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
self refresh and test mode
Fast page mode capability
All inputs, outputs and clocks fully TTL-compatible
2048 refresh cycles / 32 ms
Plastic Package:
P-SOJ-26/24 300 mil
P TSOPII-26/24 300 mil
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•
•
•
•
•
Semiconductor Group
1
1.96
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
The HYB 5117400BJ/BT is a 16MBit dynamic RAM organized as 4194304 words by 4-bits. The
HYB 5117400BJ/BT utilizes a submicron CMOS silicon gate process technology, as well as
advanced circuit techniques to provide wide operating margins, both internally and for the system
user. Multiplexed address inputs permit the HYB 5117400BJ/BT to be packaged in a standard SOJ
26/24 or TSOPII-26/24 plastic package, both with 300 mil width. These packages provide high
system bit densities and are compatible with commonly used automatic testing and insertion
equipment. System-oriented features include single + 5 V (± 10 %) power supply, direct interfacing
with high-performance logic device families such as Schottky TTL.
Ordering Information
Type
HYB 5117400BJ-50
HYB 5117400BJ-60
HYB 5117400BJ-70
HYB 5117400BT-50
HYB 5117400BT-60
HYB 5117400BT-70
Pin Names
A0 to A10
A0 to A10
RAS
OE
I/O1-I/O4
CAS
WE
Row Address Inputs
Column Address Inputs
Row Address Strobe
Output Enable
Data Input/Output
Column Address Strobe
Read/Write Input
Power Supply (+ 5 V)
Ground (0 V)
not connected
Ordering Code
Q67100-Q1086
Q67100-Q1087
Q67100-Q1088
on request
on request
on request
Package
P-SOJ-26/24 300 mil
P-SOJ-26/24 300 mil
P-SOJ-26/24 300 mil
P-TSOPII-26/24 300mil
P-TSOPII-26/24 300mil
P-TSOPII-26/24 300mil
Descriptions
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
V
CC
V
SS
N.C.
Semiconductor Group
2
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
Vcc
I/O1
I/O2
WE
RAS
N.C.
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
Vss
I/O4
I/O3
CAS
OE
A9
A8
A7
A6
A5
A4
Vss
P-SOJ-26/24
300 mil
P-TSOPII-26/24 300 mil
Pin Configuration
Semiconductor Group
3
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
I/O1 I/O2 I/O3 I/O4
WE
CAS
.
&
Data in
Buffer
No. 2 Clock
Generator
Data out
Buffer
4
OE
4
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
11
Column
Address
Buffer(11)
11
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
4
Refresh
Counter (11)
11
Row
2048
x4
Address
Buffers(11)
11
Decoder
2048
Row
Memory Array
2048x2048x4
RAS
No. 1 Clock
Generator
Voltage Down
Generator
VCC
VCC (internal)
Block Diagram
Semiconductor Group
4
HYB 5117400BJ/BT-50/-60/-70
4M x 4-DRAM
Absolute Maximum Ratings
Operating temperature range ............................................................................................0 to 70 °C
Storage temperature range.........................................................................................– 55 to 150 °C
Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,7.0) V
Power supply voltage...................................................................................................-1.0V to 7.0 V
Power dissipation..................................................................................................................... 1.0 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC Characteristics
T
A
= 0 to 70 °C,
V
SS
= 0 V,
V
CC
= 5 V
±
10 %;
t
T
= 5 ns
Parameter
Input high voltage
Input low voltage
Output high voltage (
I
OUT
= – 5 mA)
Output low voltage (
I
OUT
= 4.2 mA)
Input leakage current
(0 V
≤
V
IH
≤
Vcc + 0.3V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V
≤
V
OUT
≤
Vcc + 0.3V)
Average
V
CC
supply current:
-50 ns version
-60 ns version
-70 ns version
(RAS, CAS, address cycling:
t
RC
=
t
RC
min.)
Symbol
Limit Values
min.
max.
Vcc+0.5
0.8
–
0.4
10
10
2.4
– 0.5
2.4
–
– 10
– 10
Unit Test
Condition
V
V
V
V
µA
µA
1)
1)
1)
1)
1)
1)
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
I
CC1
–
–
–
–
–
–
–
120
110
100
2
120
110
100
mA
mA
mA
mA
mA
mA
mA
2) 3) 4)
2) 3) 4)
2) 3) 4)
Standby
V
CC
supply current (RAS = CAS =
V
IH
)
I
CC2
Average
V
CC
supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
-70 ns version
(RAS cycling, CAS =
V
I,H,
t
RC
=
t
RC
min.)
–
2) 4)
2) 4)
2) 4)
I
CC3
Semiconductor Group
5
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