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5962G9654001QXA

Description
J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, BOTTOM-BRAZED, CERAMIC, DFP-16
Categorylogic    logic   
File Size234KB,10 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

5962G9654001QXA Overview

J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, BOTTOM-BRAZED, CERAMIC, DFP-16

5962G9654001QXA Parametric

Parameter NameAttribute value
Parts packaging codeDFP
package instructionDFP,
Contacts16
Reach Compliance Codeunknown
ECCN code3A001.A.1.A
seriesAC
JESD-30 codeR-CDFP-F16
JESD-609 codee0
Logic integrated circuit typeJ-KBAR FLIP-FLOP
Number of digits2
Number of functions2
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
propagation delay (tpd)27 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class Q
Maximum seat height2.921 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose500k Rad(Si) V
Trigger typePOSITIVE EDGE
width6.731 mm
Base Number Matches1
Standard Products
UT54ACS109/UT54ACTS109
Dual J-K Flip-Flops
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS109 - SMD 5962-96540
UT54ACTS109 - SMD 5962-96541
DESCRIPTION
The UT54ACS109 and the UT54ACTS109 are dual J-K positive
triggered flip-flops. A low level at the preset or clear inputs sets
or resets the outputs regardless of the other input levels. When
preset and clear are inactive (high), data at the J and K input
meeting the setup time requirements are transferred to the out-
puts on the positive-going edge of the clock pulse. Following
the hold time interval, data at the J and K input can be changed
without affecting the levels at the outputs. The flip-flops can
perform as toggle flip-flops by grounding K and tying J high.
They also can perform as D flip-flops if J and K are tied together.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
PRE
L
H
L
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
CLK
X
X
X
L
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
OUTPUT
Q
H
L
H
L
1
PINOUTS
16-Pin DIP
Top View
CLR1
J
K1
CLK1
PRE1
Q1
Q1
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
16-Lead Flatpack
Top View
CLR1
J1
K1
CLK1
PRE1
Q1
Q1
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
LOGIC SYMBOL
Q
L
H
H
1
PRE1
J1
CLK1
K1
CLR1
PRE2
J2
CLK2
(5)
(2)
(4)
(3)
(1)
(11)
(14)
(12)
S
J1
C1
K1
R
(6)
Q1
(7)
Q1
H
Toggle
(10)
Q2
No Change
H
L
(13)
K2
(15)
CLR2
(9)
Q2
No Change
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
Note:
1. The output levels in this configuration are not guaranteed to meet the minimum
levels for V
OH
if the lows at preset and clear are near V
IL
maximum. In
addition, this configuration is nonstable; that is, it will not persist when either
preset or clear returns to its inactive (high) level.
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