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HYS72V32301GR-7-C2

Description
PC133 Registered SDRAM-Modules
Categorystorage    storage   
File Size401KB,22 Pages
ManufacturerInfineon
Websitehttp://www.infineon.com/
Download Datasheet Parametric View All

HYS72V32301GR-7-C2 Overview

PC133 Registered SDRAM-Modules

HYS72V32301GR-7-C2 Parametric

Parameter NameAttribute value
MakerInfineon
Parts packaging codeDIMM
package instructionDIMM, DIMM168
Contacts168
Reach Compliance Codeunknow
ECCN codeEAR99
access modeSINGLE BANK PAGE BURST
Maximum access time5.4 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
JESD-30 codeR-XDMA-N168
memory density2415919104 bi
Memory IC TypeSYNCHRONOUS DRAM MODULE
memory width72
Number of functions1
Number of ports1
Number of terminals168
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32MX72
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeDIMM
Encapsulate equivalent codeDIMM168
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
power supply3.3 V
Certification statusNot Qualified
refresh cycle4096
self refreshYES
Maximum standby current0.036 A
Maximum slew rate4.86 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationDUAL
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
3.3 V 168-pin Registered SDRAM Modules
PC133 128 MByte Module
PC133 256 MByte module
PC133 512 MByte Module
PC133 1 GByte Module
PC133 2 GByte Module
• 168-pin Registered 8 Byte Dual-In-Line
SDRAM Module for PC and Server main
memory applications
• One bank 16M
×
72, 32M x 72, 64M
×
72and
128M x 72, two bank 128M
×
72 and
256M x 72 organization
• Optimized for ECC applications with very low
input capacitances
• JEDEC standard Synchronous DRAMs
(SDRAM) Programmable CAS Latency, Burst
Length and Wrap Sequence (Sequential &
Interleave)
• Single + 3.3 V (
±
0.3 V) power supply
• Auto Refresh (CBR) and Self Refresh
• Performance:
speed grade
f
CK
t
CK
t
AC
f
CK
t
CK
t
AC
Clock Frequency (max.) @ CL = 3
Clock Cycle Time (min.) @ CL = 3
Clock Access Time (min.) @ CL= 3
Clock Frequency (max.) @ CL = 2
Clock Cycle Time (min.) @ CL = 2
Clock Access Time (min.) @ CL= 2
• Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• All inputs and outputs are LVTTL compatible
• Serial Presence Detect with E
2
PROM
• Utilizes SDRAMs in TSOPII-54 packages
with registers and PLL.
• Card Size: 133.35 mm
×
38.10 / 43.18 mm
with Gold contact pads and max. 4.00 / 6.80
mm thickness (JEDEC MO-161)
• These modules all fully compatible with the
current industry standard PC133 and PC100
specifications
-7
133
7.5
5.4
133
7.5
5.4
-7.5
133
7.5
5.4
100
10
6
Unit
MHz
ns
ns
MHz
ns
ns
Description
The HYS 72Vxx3xxGR-7 and -7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs)
organized as 16M
×
72, 32M x 72, 64M
×
72, 128M
×
72 and 256M x 72 high speed memory arrays designed with
Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered on-DIMM
and the design incorporates a PLL circuit for the Clock inputs. Use of an on-board register reduces capacitive
loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors
are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a serial
E
2
PROM using the 2-pin I
2
C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second
128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte
interface in a 133.35 mm long footprint.
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