CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9
FEATURES:
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•
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•
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•
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IDT72131
IDT72141
DESCRIPTION:
The IDT72131/72141 are high-speed, low power parallel-to-serial FIFOs.
These FIFOs are ideally suited to serial communications applications, tape/
disk controllers, and local area networks (LANs). These devices can be
configured with the IDTs serial-to-parallel FIFOs (IDT72132/72142) for
bidirectional serial data buffering.
The FIFO has a 9-bit parallel input port and a serial output port. Wider
and deeper parallel-to-serial data buffers can be built using multiple
IDT72131/72141 chips. IDTs unique Flexishift serial expansion logic (SOX,
NR)
makes width expansion possible with no additional components. These
FIFOs will expand to a variety of word widths including 8, 9, 16, and 32 bits.
These devices can also be directly connected for depth expansion.
Five flags are provided to monitor the FIFO. The full and empty flags
prevent any FIFO data overflow or underflow conditions. The Almost-Full
(7/8), Half-Full, and Almost-Empty (1/8) flags signal memory utilization
within the FIFO.
The IDT72131/72141 is fabricated using IDTs high-speed submicron
CMOS technology.
35ns parallel port access time, 45ns cycle time
50MHz serial port shift rate
Expandable in depth and width with no external components
Programmable word lengths including 7-9, 16-18, 32-36 bit using
Flexishift™ serial output without using any additional components
Multiple status flags: Full, Almost-Full (1/8 from full), Half-Full,
Almost- Empty (1/8 from empty), and Empty
Asynchronous and simultaneous read and write operations
Dual-Port zero fall-through architecture
Retransmit capability in single device mode
Produced with high-performance, low power CMOS technology
Available in 28-pin plastic DIP
Industrial temperature range (–40°C to +85°C)
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
W
Vcc
D
5
D
6
D
7
D
8
FL/RT
RS
EF
XO/HF
GND
Q
8
Q
7
Q
6
NR
D
0
-D
8
EF
AEF
/HF
FF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D
4
D
3
D
2
D
1
D
0
XI
SOX
FLAG
LOGIC
W
WRITE
POINTER
RAM ARRAY
2,048 x 9
4,096 x 9
NEXT READ
POINTER
NR
RS
FL/RT
RESET LOGIC
SOCP
SOCP
SO
AEF
FF
2751 drw01
XI
EXPANSION
LOGIC
XO/
SERIAL OUTPUT
CIRCUITRY
SOX
SO
Q
4
Q
6
Q
7
Q
8
Q
4
GND
2751 drw02
PLASTIC DIP (P28-1, order code: P)
TOP VIEW
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE
©
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEBRUARY 2002
1
DSC-2751/1
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
D
0
–D
8
RS
Name
Inputs
Reset
I/O
I
I
Description
Data inputs for 9-bit wide data.
When
RS
is set LOW, internal READ and WRITE pointers are set to the first location of the RAM array.
HF
and
FF
go HIGH, and
AEF
and
EF
go LOW. A reset is required before an initial WRITE after power-up.
W
must be HIGH and SOCP must be LOW during
RS
cycle.
A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up and hold
times must be adhered to with respect to the rising edge of WRITE. Data is stored in the RAM array
sequentially and independently of any ongoing read operation.
A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In both Depth
and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
To program the Serial Out data word width , connect
NR
with one of the Data Set pins (Q
4
, Q
6
, Q
7
and Q
8
).
For example,
NR
- Q
7
programs for a 8-bit Serial Out word width.
This is a dual purpose input. In the single device configuration (XI grounded), activating retransmit (FL/RT-
LOW) will set the internal READ pointer to the first location. There is no effect on the WRITE pointer.
W
must
be high and SOCP must be low before setting
FL/RT
LOW. Retransmit is not compatible with depth
expansion. In the depth expansion configuration,
FL/RT
grounded indicates the first activated device.
In the single device configuration,
XI
is grounded. In depth expansion or daisy chain expansion,
XI
is
connected to
XO
(expansion out) of the previous device.
In the Serial Output Expansion mode, the SOX pin of the least significant device is tied HIGH. The SOX pin
of all other devices is connected to the Q
8
pin of the previous device. Data is then clocked out least significant
bit first. For single device operation, SOX is tied HIGH.
Serial data is output on the Serial Output (SO) pin. Data is clocked out Least Significant Bit first. In the Serial
Width Expansion mode the SO pins are tied together and each SO pin is tristated at the end of the byte.
When
FF
goes LOW, the device is full and further WRITE operations are inhibited. When
FF
is HIGH, the
device is not full.
When
EF
goes LOW, the device is empty and further READ operations are inhibited. When
EF
is HIGH, the
device is not empty. See the description on page 6 for more details.
When
AEF
is LOW, the device is empty to 1/8 full or 7/8 to completely full. When
AEF
is HIGH, the device
is greater than 1/8 full, but less than 7/8 full.
This is a dual-purpose output. In the single device configuration (XI grounded), the device is more than half
full when
HF
is LOW. In the depth expansion configuration (XO connected to
XI
of the next device), a pulse
is sent from
XO
to
XI
when the last location in the RAM array is filled.
The appropriate Data Set pin (Q
4
, Q
6
, Q
7
and Q
8
) is connected to
NR
to program the Serial Out data word
width. For example: Q
6
-
NR
programs a 7-bit word width, Q
8
-
NR
programs a 9-bit word width, etc.
Single Power Supply of 5V.
Single ground at 0V.
W
Write
I
SOCP
NR
FL/RT
Serial Output
Clock
Next Read
First Load/
Retransmit
I
I
I
XI
SOX
Expansion In
Serial Output
Expansion
Serial Output
Full Flag
Empty Flag
Almost-Empty/
Almost-Full Flag
Expansion Out/
Half-Full Flag
Data Set
Power Supply
Ground
I
I
SO
FF
EF
AEF
XO/HF
O
O
O
O
O
Q
4
, Q
6
,
Q
7
and Q
8
V
CC
GND
O
STATUS FLAGS
Number of Words in FIFO
IDT72131
0
1-255
256-1,024
1,025-1,792
1,793-2,047
2,048
IDT72141
0
1-511
512-2,048
2,049-3,584
3,585-4,095
4,096
FF
H
H
H
H
H
L
AEF
L
L
H
H
L
L
HF
H
H
H
L
L
L
EF
L
H
H
H
H
H
2
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage with
Respect to GND
Storage
Temperature
DC Output Current
Commercial
–0.5 to +7.0
–55 to +125
–50 to +50
Unit
V
°C
mA
RECOMMENDED OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
(1)
T
A
Parameter
Commercial Supply
Voltage
Supply Voltage
Input High Voltage
Commercial
Input Low Voltage
Operating Temperature
Industrial
Min.
4.5
0
2.0
—
-40
Typ.
5.0
0
—
—
—
Max.
5.5
0
—
0.8
85
Unit
V
V
V
V
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
CAPACITANCE
Symbol
C
IN
C
OUT
Parameter
(T
A
= +25°C, f = 1.0MHz)
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
12
Unit
pF
pF
Input Capacitance
Output Capacitance
NOTE:
1. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 5.0V ± 10%, T
A
= -40°C to +85°C)
IDT72131
IDT72141
Industrial
Symbol
I
IL
(1)
I
OL
(2)
V
OH
V
OL
I
CC1
(3)
I
CC2
(3,4)
I
CC3
(3,4)
Parameter
Input Leakage Current
(Any Input)
Output Leakage Current
Output Logic "1" Voltage,
I
OUT
= –2mA
Output Logic "0" Voltage
I
OUT
= 8mA
Active Power Supply Current
Standby Current
(W =
RS
=
FL/RT
= V
IH
; SOCP = V
IL
)
Power Down Current
Min.
–1
–10
2.4
—
—
—
—
Typ.
—
—
—
—
90
8
—
Max.
1
10
—
0.4
140
12
2
Unit
µA
µA
V
V
mA
mA
mA
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2. SOCP
≤
V
IL
, 0.4
≤
V
OUT
≤
V
CC
.
3. Tested with outputs open (I
OUT
= 0).
4.
RS
=
FL/RT
=
W
= V
CC
-0.2V; SOCP
≤
0.2V; all other inputs = V
CC
- 0.2V or GND + 0.2V, which toggle at 20 MHz.
3
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 5.0V ± 10%, T
A
= -40°C to +85°C)
Industrial
IDT72131L35
IDT72141L35
Min.
Max.
—
—
18
0
45
35
10
—
—
—
35
5
5
—
5
8
—
—
—
35
45
35
35
10
—
—
20
20
45
35
35
10
—
—
35
10
15
22.2
50
—
—
—
—
—
30
30
45
—
16
22
18
—
—
20
30
30
—
—
—
—
—
45
45
—
—
—
—
—
—
35
35
—
—
—
IDT72131L50
IDT72141L50
Min.
Max.
—
—
30
5
65
50
15
—
—
—
50
5
5
—
5
10
—
—
—
50
65
50
50
15
—
—
35
35
65
50
50
15
—
—
50
10
15
15
40
—
—
—
—
—
45
45
65
—
26
22
18
—
—
25
40
40
—
—
—
—
—
65
65
—
—
—
—
—
—
50
50
—
—
—
Symbol
t
S
t
SOCP
t
DS
t
DH
t
WC
t
WPW
t
WR
t
WEF
t
WFF
t
WF
t
WPF
t
SOHZ
t
SOLZ
t
SOPD
t
SOX
t
SOCW
t
SOCEF
t
SOCFF
t
SOCF
t
REFSO
t
RSC
t
RS
t
RSS
t
RSR
t
RSF1
t
RSF2
t
RSQL
t
RSQH
t
RTC
t
RT
t
RTS
t
RTR
t
XOL
t
XOH
t
XI
t
XIR
t
XIS
NOTE:
Parameter
Parallel Shift Frequency
Serial-Out Shift Frequency
Data Set-up Time
Data Hold Time
Write Cycle Time
Write Pulse Width
Write Recovery Time
Write High to
EF
HIGH
Write Low to
FF
LOW
Write Low to Transitioning
HF, AEF
Write Pulse Width After
FF
HIGH
SOCP Rising Edge to SO at High-Z
(1)
SOCP Rising Edge to SO at Low-Z
(1)
SOCP Rising Edge to Valid Data on SO
SOX Set-up Time to SOCP Rising Edge
Serial In Clock Width HIGH/LOW
SOCP Rising Edge (Bit 0 - Last Word) to
EF
LOW
SOCP Rising Edge to
FF
HIGH
SOCP Rising Edge to
HF, AEF,
HIGH
Recovery Time SOCP After
EF
HIGH
Reset Cycle Time
Reset Pulse Width
Reset Set-up Time
Reset Recovery Time
Reset to
EF
and
AEF
LOW
Reset to
HF
and
FF
HIGH
Reset to Q LOW
Reset to Q HIGH
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Set-up Time
Retransmit Recovery Time
Read/Write to
XO
LOW
Read/Write to
XO
HIGH
XI
Pulse Width
XI
Recovery Time
XI
Set-up Time
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARALLEL INPUT TIMINGS
SERIAL OUTPUT TIMINGS
RESET TIMINGS
RETRANSMIT TIMINGS
DEPTH EXPANSION MODE TIMINGS
1. Guaranteed by design minimum times, not tested.
4
IDT72131/72141 CMOS PARALLEL-TO-SERIAL FIFO
2,048 x 9 and 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
5V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure A
680Ω
D.U.T.
1.1KΩ
30pF*
2751 drw03
or equivalent circuit
Figure A. Output Load
*Including jig and scope capacitances
FUNCTIONAL DESCRIPTION
PARALLEL DATA INPUT
The data is written into the FIFO in parallel through the D0-8 input data
lines. A write cycle is initiated on the falling edge of the Write (W) signal
provided the Full Flag (FF) is not asserted. If the
W
signal changes from
HIGH-to-LOW and the Full-Flag (FF) is already set, the write line is inhibited
internally from incrementing the write pointer and no write operation occurs.
Data set-up and hold times must be met with respect to the rising edge
of Write. The data is written to the RAM at the write pointer. On the rising
edge of
W,
the write pointer is incremented. Write operations can occur
simultaneously or asynchronously with read operations.
SERIAL DATA OUTPUT
The serial data is output on the SO pin. The data is clocked out on the
rising edge of SOCP providing the Empty Flag (EF) is not asserted. If the
Empty Flag is asserted then the next data word is inhibited from moving to
the output register and being clocked out by SOCP. NOTE: SOCP should
not be clocked once the last bit of the last word has been clocked out. If it
is, then two things will occur. One, the SO pin will go High-Z and two, SOCP
will be out of sync with Next Read (NR).
The serial word is shifted out Least Significant Bit first, that is the first bit
will be D0, then D1 and so on up to the serial word width. The serial word
width must be programmed by connecting the appropriate Data Set line
(Q4, Q6, Q7 or Q8) to the
NR
input. The Data Set lines are taps off a digital
delay line. Selecting one of these taps, programs the width of the serial word
to be read and shifted out.
t
RSC
t
RS
RS
t
RSS
W
t
RSF1
AEF, EF
t
RSF2
HF, FF
t
RSS
SOCP
t
RSQL
Q
4
, Q
6
, Q
7
, Q
8
2751 drw04
t
RSR
t
RSR
t
RSQH
Figure 1. Reset
5
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