AD805 datasheet, PDF - EEWORLD Datasheet

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AD805: DescriptionDATA RETIMING PHASE LOCKED LOOP; File Size301KB，11 Pages; ManufacturerADI; Websitehttps://www.analog.com

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AD805 Overview

DATA RETIMING PHASE LOCKED LOOP

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FEATURES

155 Mbps Clock Recovery and Data Retiming

Permits CCITT G.958 Type A Jitter Tolerance

Permits CCITT G.958 Type B Jitter Transfer

Random Jitter: 0.6 rms

Pattern Jitter: Virtually Eliminated

Jitter Peaking: Fundamentally None

Acquisition: 30 Bit Periods

Accepts NRZ Data without Preamble

Single Supply Operation: –5.2 V or +5 V

10 KH ECL Compatible

DATA

INPUT

VOLTAGE

CONTROLLED

PHASE

SHIFTER

Data Retiming

Phase-Locked Loop

AD805*

CLOCK RECOVERY AND

DATA RETIMING APPLICATION

PHASE

DETECTOR

LOOP

FILTER

GAIN

OBS

PRODUCT DESCRIPTION

RETIMING

MODULE

VCXO

(EXTERNAL)

RECOVERED

CLOCK

AD805

The AD805 is a data retiming phase-locked loop designed for

use with a Voltage-Controlled Crystal Oscillator (VCXO) to

perform clock recovery and data retiming on Nonreturn to Zero

(NRZ) data. The circuit provides clock recovery and data

retiming on standard telecommunications STS-3 or STM-1

data (155.52 Mbps). A Vectron C0-434Y Series VCXO circuit

is used with the AD805 for specification purposes. Similar

circuit performance can be obtained using other commercially

available VCXO circuits. The AD805-VCXO circuit used for

clock recovery and data retiming can also be used for large

factor frequency multiplication.

The AD805-VCXO circuit meets or exceeds CCITT G.958

regenerator specifications for STM-I Type A jitter tolerance and

STM-1 Type B jitter transfer. The simultaneous Type A, wide-

band jitter tolerance and Type B, narrow-band jitter transfer

allows the use of the AD805-VCXO circuit in a regenerative

application to overcome optical line system interworking limit-

ations based on signal retiming using Type A passive tuned

device technology such as Surface-Acoustic-Wave (SAW) or

dielectric resonator filters, with Type B active devices such as

Phase-Locked Loops (PLLs).

The circuit VCXO provides a stable and accurate clock fre-

quency signal with or without input data. The AD805 works

with the VCXO to dynamically adjust the recovered clock fre-

quency to the frequency associated with the input data. This

frequency control loop tracks any low frequency component of

jitter on the input data. Since the circuit uses the VCXO for

clock recovery, it has a high Q for excellent wideband jitter at-

tenuation. The jitter transfer characteristic of the circuit is with-

in the jitter transfer requirements for a CCITT G.958 STM-1

Type B regenerator, which has a corner frequency of 30 kHz.

The AD805 overcomes the higher frequency jitter tolerance

limitations associated with traditional high Q, PLL based clock

and data recovery circuits through the use of its data retiming

loop. This loop, made up of the AD805’s voltage-controlled

*Protected

by U.S. Patent No. 5,036,298

OLE

RETIMED

DATA

phase shifter, phase detector, and loop filter, act to align input

data phase errors to the stable recovered clock provided by the

VCXO. The range of the voltage-controlled phase shifter, at

least 2 Unit Intervals (UI), and the bandwidth of this loop, at

roughly 3 MHz, provide the circuit with its wideband jitter

tolerance characteristic.

The circuit can acquire lock to input data very quickly, within

44 bit periods, due to the accuracy of the VCXO and the action

of the data retiming loop. Typical integrated second-order PLLs

take at least several thousand bit periods to acquire lock. This is

due to their having a wide tuning range VCO. Decreasing the

loop damping of a traditional second-order PLL shortens the

length of the circuit’s acquisition time, but at the expense of

greater jitter peaking.

The AD805-VCXO circuit is a second- order PLL that has no

jitter peaking. The zero used to stabilize the control loop of the

traditional second-order PLL effects the closed-loop transfer

function, causing jitter peaking in the jitter transfer function. In

the AD805-VCXO circuit, the zero needed to stabilize the loop

is implemented in the feedback path, in the voltage-controlled

phase shifter. Placing the zero in the feedback path results in

fundamentally no jitter peaking since the zero is absent from the

closed-loop transfer function.

Output jitter, determined primarily by the VCXO, is a very low

0.6° rms. Jitter due to variations in input data density, pattern

jitter, is virtually eliminated in the circuit due to the AD805’s

patented phase detector.

The data retiming loop of the AD805 can be used with a passive

tuned circuit (155.52 MHz) such as a bandpass or a SAW filter

for clock recovery and data retiming. The data retiming loop

acts to servo the phase of the input data to the phase of the

recovered clock from the passive tuned circuit in this type of

application (see APPLICATIONS).

The AD805 uses 10 KH ECL levels and consumes 375 mW

from a +5 V or a –5.2 V supply. The device is specified for

operation over the industrial temperature range of –40°C to

+85°C and is available in a 20-pin plastic DIP.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

World Wide Web Site: http://www.analog.com

Fax: 617/326-8703

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

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