Integrated
Circuit
Systems, Inc.
ICS8302I-01
L
OW
S
KEW
, 1-
TO
-2 LVCMOS / LVTTL
F
ANOUT
B
UFFER W
/ C
OMPLEMENTARY
O
UTPUT
F
EATURES
• Complementary LVCMOS / LVTTL output
• LVCMOS / LVTTL clock input accepts LVCMOS
or LVTTL input levels
• Maximum output frequency: 250MHz
• Output skew: 165ps (maximum)
• Part-to-part skew: 800ps (maximum)
• Small 8 lead SOIC package saves board space
• Full 3.3V or 3.3V core/2.5V output supply modes
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free compliant
packages
G
ENERAL
D
ESCRIPTION
T h e I C S 8 3 0 2I-01 i s a l ow s kew, 1 - t o - 2
LVCMOS/LVTTL Fanout Buffer w/Complemen-
HiPerClockS™
tary Output a n d a m e m b e r o f t h e
HiPerClock S ™family of High Performance
Clock Solutions from ICS. The ICS8302I-01
has a single ended clock input. The single ended clock
input accepts LVCMOS or LVTTL input levels. T h e
ICS8302I-01 is characterized at full 3.3V for input V
DD
,
and mixed 3.3V and 2.5V for output operating supply
modes (V
DDO
). Guaranteed output and part-to-part skew
characteristics make the ICS8302I-01 ideal for clock
distribution applications demanding well defined
performance and repeatability.
IC
S
B
LOCK
D
IAGRAM
Q
CLK
nQ
P
IN
A
SSIGNMENT
V
DDO
V
DD
CLK
GND
1
2
3
4
8
7
6
5
Q
GND
V
DDO
nQ
ICS8302I-01
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
8302AMI-01
www.icst.com/products/hiperclocks.html
1
REV. A NOVEMBER 2, 2005
Integrated
Circuit
Systems, Inc.
ICS8302I-01
L
OW
S
KEW
, 1-
TO
-2 LVCMOS / LVTTL
F
ANOUT
B
UFFER W
/ C
OMPLEMENTARY
O
UTPUT
Type
Description
Output supply pins.
Power supply pin.
Pulldown
LVCMOS / LVTTL clock input.
Power supply ground.
Complementary clock output. LVCMOS / LVTTL interface levels.
Clock output. LVCMOS / LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 6
2
3
4,7
5
8
Name
V
DDO
V
DD
CLK
GND
nQ
Q
Power
Power
Input
Power
Output
Output
NOTE:
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pulldown Resistor
Output Impedance
5
V
DD
, V
DDO
= 3.465V
V
DD
= 3.465V, V
DDO
= 2.625V
Test Conditions
Minimum
Typical
4
22
16
51
7
12
Maximum
Units
pF
pF
pF
kΩ
Ω
8302AMI-01
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 2, 2005
Integrated
Circuit
Systems, Inc.
ICS8302I-01
L
OW
S
KEW
, 1-
TO
-2 LVCMOS / LVTTL
F
ANOUT
B
UFFER W
/ C
OMPLEMENTARY
O
UTPUT
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Power Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
3.465
2.625
13
4
Units
V
V
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CL K
CLK
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 3.465, 50
Ω
to V
DDO
/2
V
OH
Output High Voltage
V
DDO
= 3.465, I
OH
= -100µA
V
DDO
= 2.625, 50
Ω
to V
DDO
/2
V
DDO
= 2.625, I
OH
= -100µA
V
DDO
= 3.465, 50
Ω
to V
DDO
/2
V
OL
Output Low Voltage
V
DDO
= 3.465, I
OL
= 100µA
V
DDO
= 2.625, 50
Ω
to V
DDO
/2
V
DDO
= 2.625, I
OL
= 100µA
-5
2.6
2.9
1.8
2.2
0. 5
0.2
0. 5
0.2
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
µA
V
V
V
V
V
V
V
V
8302AMI-01
www.icst.com/products/hiperclocks.html
3
REV. A NOVEMBER 2, 2005
Integrated
Circuit
Systems, Inc.
ICS8302I-01
L
OW
S
KEW
, 1-
TO
-2 LVCMOS / LVTTL
F
ANOUT
B
UFFER W
/ C
OMPLEMENTARY
O
UTPUT
Test Conditions
Minimum
1.8
Typical
Maximum
250
2.7
165
800
20% to 80%
IJ 133MHz
300
45
800
55
60
Units
MHz
ns
ps
ps
ps
%
%
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
133MHz < ƒ
≤
250MHz
40
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
IJ 133MHz
100
45
1.9
Test Conditions
Minimum
Typical
Maximum
250
2.9
250
900
850
55
60
Units
MHz
ns
ps
ps
ps
%
%
133MHz < ƒ
≤
250MHz
40
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8302AMI-01
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 2, 2005
Integrated
Circuit
Systems, Inc.
ICS8302I-01
L
OW
S
KEW
, 1-
TO
-2 LVCMOS / LVTTL
F
ANOUT
B
UFFER W
/ C
OMPLEMENTARY
O
UTPUT
P
ARAMETER
M
EASUREMENT
I
NFORMATION
1.65V±5%
2.05V±5% 1.25V±5%
V
DD
,
V
DDO
SCOPE
Qx
V
DD
V
DDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V±5%
-1.25V±5%
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
V
DD
3.3V/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
V
Q
CLK
2
V
DDO
DDO
2
V
Q
nQ
V
2
DDO
nQ
DDO
2
2
t
PD
tsk(o)
P
ROPAGATION
D
ELAY
PART 1
Q
PART 2
Q
nQ
V
V
DD
O
UTPUT
S
KEW
80%
20%
t
R
t
F
80%
20%
2
V
DDO
2
DDO
Clock
Outputs
2
tsk(pp)
P
ART
-
TO
-P
ART
S
KEW
nQ
V
DDO
V
DDO
2
O
UTPUT
R
ISE
/F
ALL
T
IME
Q
2
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
8302AMI-01
www.icst.com/products/hiperclocks.html
5
REV. A NOVEMBER 2, 2005
京公网安备 11010802033920号
EEWORLD
