PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843252
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
F
EATURES
• Two 3.3V differential LVPECL output pairs
• Using a 19.53125MHz or 25MHz crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
• Crystal oscillator interface
• VCO range: 490MHz to 680MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.47ps (typical)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
• Available in both standard and lead-free RoHS-compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS843252 is a 2 differential output LVPECL
Synthesizer designed to generate Ethernet refer-
HiPerClockS™
ence clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from ICS. Using a 19.53125MHz or
25MHz, 18pF parallel resonant crystal, the following frequen-
cies can be generated based on the settings of 4 frequency
select pins (SEL[A1:A0], SEL[B1:B0]): 625MHz, 312.5MHz,
156.25MHz, and 125MHz.
IC
S
The two banks have their own dedicated frequency select
pins and can be independently set for the frequencies
mentioned above. The ICS843252 ICS’ 3rd generation
low phase noise VCO technology and can achieve 1ps or
lower typical rms phase jitter, easily meeting Ethernet
jitter requirements. The ICS843252 is packaged in a small
16-pin TSSOP package.
B
LOCK
D
IAGRAM
SELA[0:1}
Pullup
2
00
01
10
11
00
01
10
11
÷1
÷2
÷3
÷4
(default)
÷2
÷4
÷5
÷8
(default)
P
IN
A
SSIGNMENT
nQB
QB
V
CCO
_
B
SELB1
SELB0
V
CCO
_
A
QA
nQA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTAL_IN
XTAL_OUT
V
EE
SELA1
SELA0
V
CC
V
CCA
FB_SEL
QA
nQA
XTAL_IN
XTAL_OUT
OSC
Phase
Detector
VCO
490MHz - 680MHz
QB
nQB
Feedback Divider
0 = ÷25
(default)
1 = ÷32
ICS843252
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
FB_SEL
Pulldown
SELB[0:1}
Pullup
2
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843252AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 9, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843252
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
Τψπ ε
Δ ε σχριπ τιο ½
Differential clock outputs. LVPECL interface levels.
Output supply pin for QB, nQB outputs.
Division select pins for Bank B. Default = High.
LVCMOS/LVTTL interface levels.
Output supply pin for QA output.
Differential clock outputs. LVPECL interface levels.
Feedback divide select. When Low (default), the feedback divider is set
for ÷25. When HIGH, the feedback divider is set for ÷32.
LVCMOS/LVTTL interface levels.
Analog supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Νυ μ β ε ρ
1, 2
3
4,
5
6
7, 8
9
10
11
12,
13
14
Ναμ ε
nQB, QB
V
CCO_B
SELB1,
SELB0
V
CCO_A
QA, nQA
FB_SEL
V
CCA
Power
Input
Power
Output
Input
Power
Pulldown
Pullup
Output
Power
Core supply pin.
V
CC
SELA0,
Division select pins for Bank A. Default = HIGH.
Input
Pullup
SELA1
LVCMOS/LVTTL interface levels.
Power
Negative supply pin.
V
EE
XTAL_OUT,
Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
15, 16
Input
XTAL_IN
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
843252AG
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843252
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
89°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A,
V
CCO_B
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO_A,
V
CCO_B
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
122
7
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
FB_SEL
SELA0, SELA1,
SELB0, SELB1
FB_SEL
SELA0, SELA1,
SELB0, SELB1
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IL
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO_B
- 2V.
843252AG
www.icst.com/products/hiperclocks.html
5
REV. A NOVEMBER 9, 2005
FPGA/CPLD
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