PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
F
EATURES
•
6 LVPECL outputs
•
Crystal oscillator interface
•
Output frequency: 75MHz or 150MHz
•
Crystal input frequency: 25MHz
•
Cycle-to-cycle jitter: 20ps (typical)
•
RMS phase jitter at 150MHz, using a 25MHz crystal
(899.8KHz to 20MHz): TBD
•
Phase noise:
Offset
100Hz ...............
1KHz ...............
10KHz ...............
100KHz ...............
Noise Power
TBD
TBD
TBD
TBD
G
ENERAL
D
ESCRIPTION
The ICS84326 is a Crystal-to-3.3V LVPECL Clock
Synthesizer/Fanout Buffer designed for Serial
HiPerClockS™
Attached SCSI applications and is a member of
the HiperClockS family of High Performance Clock
Solutions from ICS. Using a 25MHz crystal, the
6 LVPECL outputs can be set for either 75MHz or 150MHz
using the frequency select pins. The low jitter/low phase noise
characteristics make it an ideal clock source for use in Serial
Attached SCSI applications or for other applications which
require a 75MHz or 150MHz reference clock.
,&6
F
UNCTION
T
ABLE
Inputs
MR
1
0
0
F_SEL
X
0
1
Output Frequency
F_OUT
LOW
75MHz
150MHz
•
Full 3.3V or 3.3V core, 2.5V supply mode
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CCO
F_SEL
nc
MR
XTAL1
XTAL2
nc
V
CCA
V
CC
PLL_SEL
V
EE
V
CCO
XTAL1
OSC
XTAL2
0
1
6
Output
Divider
PLL
/
6
/
Q0:Q5
nQ0:nQ5
Feedback
Divider
ICS84326
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
MR
PLL_SEL
F_SEL
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84326AM
www.icst.com/products/hiperclocks.html
1
REV. A MARCH 10, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
Type
Output
Output
Output
Output
Output
Output
Power
Power
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pins.
Core supply pin.
Negative supply pin.
Selects between the PLL and crystal inputs as the input to the
dividers. When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2.
LVCMOS / LVTTL interface levels.
Analog supply pin.
No connect.
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs Qx to go low, and the inver ted
Pulldown
outputs nQx to go high. When logic LOW, the internal dividers and
the outputs are enabled. LVCMOS / LVTTL interface levels.
Pullup
Output frequency select pin. LVCMOS / LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 6
7, 8
9, 10
11, 12
13, 24
16
14
15
17
18, 22
19, 20
21
23
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
V
CCO
V
CC
V
EE
PLL_SEL
V
CCA
nc
XTAL2, XTAL1
MR
F_SEL
Input
Power
Unused
Input
Input
Input
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
51
51
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
KΩ
KΩ
84326AM
www.icst.com/products/hiperclocks.html
2
REV. A MARCH 10, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
4.6V
-0.5V to V
CC
+ 0.5 V
-0.5V to V
CCO
+ 0.5V
50°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
140
20
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
PLL_SEL, MR,
F_SEL
PLL_SEL, MR,
F_SEL
MR
PLL_SEL, F_SEL
MR
PLL_SEL, F_SEL
Test Conditions
Minimum
2
-0.3
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 1.0
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
84326AM
www.icst.com/products/hiperclocks.html
3
REV. A MARCH 10, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3.3
3.3
2.5
140
20
Maximum
3.465
3.465
2.625
Units
V
V
V
mA
mA
T
ABLE
3D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
T
ABLE
3E. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
PLL_SEL, MR,
F_SEL
PLL_SEL, MR,
F_SEL
MR
PLL_SEL, F_SEL
MR
PLL_SEL, F_SEL
Test Conditions
Minimum
2
-0.3
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
T
ABLE
3F. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 1.0
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pf parallel resonant crystal.
Test Conditions
Minimum
Typical
Fundamental
25
70
7
MHz
Ω
pF
Maximum
Units
84326AM
www.icst.com/products/hiperclocks.html
4
REV. A MARCH 10, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
Test Conditions
Minimum
75
20
TBD
50
20% to 80%
200
50
1
700
Typical
Maximum
150
Units
MHz
ps
ps
ps
ps
%
ms
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
F
OUT
Output Frequency
Cycle-to-Cycle Jitter ; NOTE 2
Period Jitter, RMS
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
t
jit(cc)
t
jit(per)
t
sk(o)
t
R
/ t
F
odc
t
LOCK
PLL Lock Time
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
F
OUT
Output Frequency
Cycle-to-Cycle Jitter ; NOTE 2
Period Jitter, RMS
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
50
1
Test Conditions
Minimum
75
20
TBD
35
700
Typical
Maximum
150
Units
MHz
ps
ps
ps
ps
%
ms
t
jit(cc)
t
jit(per)
t
sk(o)
t
R
/ t
F
odc
t
LOCK
PLL Lock Time
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
84326AM
www.icst.com/products/hiperclocks.html
5
REV. A MARCH 10, 2003
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