PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844252-04
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS844252-04 is a 10Gb/12Gb Ethernet
Clock Generator and a member of the
HiPerClockS™
HiPerClocks
TM
family of high perfor mance
devices from ICS. The ICS844252-04 can
synthesize 10 Gigabit Ethernet and 12 Gigabit
Ethernet with a 25MHz crystal. It can also generate SATA
and 10Gb Fibre Channel reference clock frequencies with
the appropriate choice of crystals. The ICS844252-04 has
excellent phase jitter performance and is packaged in a
small 16-pin TSSOP, making it ideal for use in systems with
limited board space.
F
EATURES
•
Two differential LVDS outputs
•
Crystal oscillator interface designed for
18pF parallel resonant crystals
•
Crystal input frequency range: 19.33MHz - 30MHz
•
Output frequency range: 145MHz - 187.5MHz
•
VCO frequency range: 580MHz - 750MHz
•
RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
0.36ps (typical)
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Available in both standard and lead-free compliant
packages
IC
S
C
ONFIGURATION
T
ABLE
Crystal Frequency
(MHz)
25
25
WITH
25MH
Z
C
RYSTAL
N Output Divide
4
4
Output Frequency
(MHz)
187.5
156.25
Application
12 Gigabit Ethernet
10 Gigabit Ethernet
Inputs
Feedback VCO Frequency
Divide
(MHz)
30
750
25
WITH
625
C
ONFIGURATION
T
ABLE
Crystal Frequency
(MHz)
20
21.25
24
25.5
30
S
ELECTABLE
C
RYSTALS
N Output Divide
4
4
4
4
4
Output Frequency
(MHz)
150
159.375
150
159.375
187.5
Application
SATA
10 Gigabit Fibre Channel
SATA
10 Gigabit Fibre Channel
12 Gigabit Ethernet
Inputs
Feedback VCO Frequency
Divide
(MHz)
30
600
30
25
25
25
637.5
60 0
637.5
750
B
LOCK
D
IAGRAM
OE
nPLL_SEL
REF_CLK
Pullup
Pulldown
P
IN
A
SSIGNMENT
D
Q
LE
nQ1
Q1
V
DDO
OE
nPLL_SEL
V
DDO
Q0
nQ0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTAL_IN
XTAL_OUT
GND
REF_CLK
CLK_SEL
V
DD
V
DDA
FREQ_SEL
Pulldown
1
1
XTAL_IN
OSC
XTAL_OUT
CLK_SEL
Pulldown
0
Phase
Detector
VCO
580MHz-750MHz
DIV. N
÷4
0
Q0
nQ0
Q1
nQ1
ICS844252-04
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
0 = ÷25
(default)
1 = ÷30
FREQ_SEL
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
844252AG-04
www.icst.com/products/hiperclocks.html
REV. A JANUARY 26, 2006
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844252-04
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 6
4
Name
nQ1, Q1
V
DDO
OE
Power
Input
Type
Output
Description
Differential clock outputs. LVDS interface levels.
Output supply pins.
Output enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
Pullup
LVCMOS/LVTTL interface levels.
Selects between the PLL and reference clock as input to the divider.
Pulldown When Low, selects PLL. When High, selects reference clock.
LVCMOS/LVTTL interface levels.
Differential clock outputs. LVDS interface levels.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Pulldown
Clock select input. When Low, selects cr ystal inputs. When High,
selects REF_CLK. LVCMOS/LVTTL interface levels.
Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
5
7, 8
9
10
11
12
13
14
nPLL_SEL
Q0, nQ0
FREQ_SEL
V
DDA
V
DD
CLK_SEL
REF_CLK
Input
Output
Input
Power
Power
Input
Input
GN D
Power
Power supply ground.
Cr ystal oscillator interface. XTAL_IN is the input,
XTAL_OUT,
15, 16
Input
XTAL_OUT is the output.
XTAL_IN
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characterristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
844252AG-04
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844252-04
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
89°C/W (0 lfpm)
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
70
11
40
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
REF_CLK,
CLK_SEL,
FREQ_SEL,
nPLL_SEL
OE
REF_CLK,
CLK_SEL,
FREQ_SEL,
nPLL_SEL
OE
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IH
Input High Current
I
IL
Input Low Current
T
ABLE
3C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
400
40
1.25
50
Maximum
Units
mV
mV
V
mV
844252AG-04
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844252-04
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS C
LOCK
G
ENERATOR
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
19.33
Test Conditions
Minimum
Typical
Fundamental
30
50
7
1
MHz
Ω
pF
mW
Maximum
Units
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
OUT
t
sk(o)
Parameter
Output Frequency
Output Skew; NOTE 1, 2
156.25MHz @ Integration Range:
1.875MHz - 20MHz
159.375MHz @ Integration Range:
1.875MHz - 20MHz
187.5MHz @ Integration Range:
1.875MHz - 20MHz
20% to 80%
Test Conditions
Minimum
145
TBD
0.36
0.38
0.38
375
Typical
Maximum
187.5
Units
MH z
ps
ps
ps
ps
ps
%
t
jit(Ø)
RMS Phase Jitter (Random);
NOTE 3
t
R
/ t
F
Output Rise/Fall Time
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots following this section.
844252AG-04
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844252-04
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS C
LOCK
G
ENERATOR
T
YPICAL
P
HASE
N
OISE
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
AT
156.25MH
Z
➤
Gb Ethernet Filter
156.25MHz
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.36ps (typical)
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
➤
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
➤
Phase Noise Result by adding a
Gb Ethernet Filter Filter to raw data
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
844252AG-04
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 26, 2006
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