®
FAST CMOS
OCTAL FLIP-FLOP
WITH MASTER RESET
DESCRIPTION:
IDT54/74FCT273
IDT54/74FCT273A
IDT54/74FCT273C
Integrated Device Technology, Inc.
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
IDT54/74FCT273 equivalent to FAST™ speed;
IDT54/74FCT273A 45% faster than FAST
IDT54/74FCT273C 55% faster than FAST
Equivalent to FAST output drive over full temperature
and voltage supply extremes
I
OL
= 48mA (commercial) and 32mA (military)
CMOS power levels (1mW typ. static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than FAST
(5µA max.)
Octal D flip-flop with Master Reset
JEDEC standard pinout for DIP and LCC
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT273/A/C are octal D flip-flops built using
an advanced dual metal CMOS technology. The IDT54/
74FCT273/A/C have eight edge-triggered D-type flip-flops
with individual D inputs and O outputs. The common buffered
Clock (CP) and Master Reset ( ) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s O
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the
input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
MR
MR
FUNCTIONAL BLOCK DIAGRAM
D
0
CP
D
CP
R
D
MR
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
2558 drw 01
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Q
D
CP
Q
R
D
D
CP
Q
R
D
D
CP
Q
R
D
D
CP
Q
R
D
D
CP
Q
R
D
D
CP
Q
R
D
D
CP
Q
R
D
PIN CONFIGURATIONS
D
0
O
0
MR
Vcc
O
7
3 2
4
5
6
7
8
O
3
GND
CP
O
4
D
4
MR
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
P20-1
D20-1
SO20-2
&
E20-1
17
16
15
14
13
12
11
Vcc
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
INDEX
D
1
O
1
O
2
D
2
D
3
L20-2
20 19
18
1
17
16
15
14
9 10 11 12 13
D
7
D
6
O
6
O
5
D
5
2558 drw 02
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992
Integrated Device Technology, Inc.
MAY 1992
DSC-4609/2
7.10
1
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
D
N
Description
Data Input
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
2558 tbl 05
FUNCTION TABLE
Operating Mode
Reset (Clear)
Load “1”
Load “0”
MR
CP
O
N
MR
L
H
H
Inputs
CP
X
↑
↑
D
N
X
h
l
Outputs
O
N
L
H
L
NOTES:
2558 tbl 06
H = HIGH voltage level steady-state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don’t care
↑
= LOW-to-HIGH clock transition
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
Rating
Terminal Voltage
with Respect
to GND
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions Typ. Max.
V
IN
= 0V
V
OUT
= 0V
6
8
10
12
Unit
pF
pF
V
TERM(3)
Terminal Voltage
with Respect
to GND
T
A
T
BIAS
T
STG
P
T
I
OUT
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output Current
–0.5 to V
CC
–0.5 to V
CC
V
NOTE:
2558 tbl 02
1. This parameter is guaranteed by characterization data and not tested.
0 to +70
–55 to +125
–55 to +125
0.5
120
–55 to +125
–65 to +135
–65 to +150
0.5
120
°C
°C
°C
W
mA
NOTES:
2558 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
7.10
2
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
IH
I
IL
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Vcc = Min., I
N
= –18mA
Vcc = Max.
(3)
, V
O
= GND
Vcc = 3V, V
IN
= V
LC
or V
HC
, I
OH
= –32µA
Vcc = Min.
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
I
OH
= –300µA
I
OH
= –12mA MIL.
I
OH
= –15mA COM’L.
Vcc = 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300µA
Vcc = Min.
V
IN
= V
IH
or V
IL
I
OL
= 300µA
I
OL
= 32mA MIL.
I
OL
= 48mA COM’L.
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
Min.
2.0
—
—
—
—
—
—
–60
V
HC
V
HC
2.4
2.4
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
–0.7
–120
V
CC
V
CC
4.3
4.3
GND
GND
0.3
0.3
Max.
—
0.8
5
5
(4)
–5
(4)
–5
–1.2
—
—
—
—
—
V
LC
V
LC(4)
0.5
0.5
2558 tbl 03
Unit
V
V
µA
V
mA
V
V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.10
3
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Symbol
I
CC
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
Vcc = Max.
V
IN
≥
V
HC
; V
IN
≤
V
LC
Vcc = Max.
V
IN
= 3.4V
(3)
Vcc = Max.
Outputs Open
= V
CC
One Input Toggling
50% Duty Cycle
V
IN
≥
V
HC
V
IN
≤
V
LC
Min.
—
—
—
Typ.
(2)
0.2
0.5
0.15
Max.
1.5
2.0
0.25
Unit
mA
mA
mA/MHz
MR
I
C
Total Power Supply Current
(6)
Vcc = Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
= V
CC
One Bit Toggling
at f
i
= 5MHz
50% Duty Cycle
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
1.7
4.0
mA
MR
—
2.2
6.0
Vcc = Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
= V
CC
Eight Bits Toggling
f
i
= 2.5MHz
50% Duty Cycle
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
4.0
7.8
(5)
MR
—
6.2
16.8
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2558 tbl 04
7.10
4
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT273
Com’l.
Symbol
t
PLH
t
PHL
t
PHL
t
SU
t
H
t
W
t
W
t
REM
Parameter
Propagation Delay
Clock to Output
Propagation Delay
to Output
Mil.
IDT54/74FCT273A
Com’l.
Mil.
IDT54/74FCT273C
Com’l.
Mil.
Condition
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min
.
(2)
Max.
Unit
C
L
= 50 pF
2.0 13.0
2.0 15.0
2.0
7.2
2.0
8.3
2.0
5.8
2.0 6.5
ns
R
L
= 500Ω
2.0
3.0
2.0
7.0
7.0
4.0
13.0
—
—
—
—
—
2.0
3.5
2.0
7.0
7.0
5.0
15.0
—
—
—
—
—
2.0
2.0
1.5
6.0
6.0
2.0
7.2
—
—
—
—
—
2.0
2.0
1.5
6.0
6.0
2.5
8.3
—
—
—
—
—
2.0
2.0
1.5
6.0
6.0
2.0
6.1
—
—
—
—
—
2.0
2.0
1.5
6.0
6.0
2.5
6.8
—
—
—
—
—
ns
ns
ns
ns
ns
ns
2558 tbl 07
MR
Set-up Time HIGH
or LOW Data to CP
Hold Time HIGH
or LOW Data to CP
Clock Pulse Width
HIGH or LOW
MR
Pulse Width
LOW
Recovery Time
to CP
MR
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
7.10
5
Embedded System
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