DPDD16MX16TSBY5-DP-XX7520 datasheet, PDF

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DPDD16MX16TSBY5-DP-XX7520: DescriptionDDR DRAM Module, 16MX16, CMOS, LEADLESS, STACK, TSOP-66; Categorystorage storage; File Size729KB，2 Pages; ManufacturerB&B Electronics Manufacturing Company

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DPDD16MX16TSBY5-DP-XX7520 Overview

DDR DRAM Module, 16MX16, CMOS, LEADLESS, STACK, TSOP-66

DPDD16MX16TSBY5-DP-XX7520 Parametric

Parameter Name	Attribute value
Maker	B&B Electronics Manufacturing Company
Parts packaging code	DMA
package instruction	,
Contacts	66
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N66
memory density	268435456 bit
Memory IC Type	DDR DRAM MODULE
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	66
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
organize	16MX16
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
self refresh	YES
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Terminal form	NO LEAD
Terminal location	DUAL
Base Number Matches	1

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256 Megabit CMOS DDR SDRAM

DPDD16MX16TSBY5

ADVANCED INFORMATION

DESCRIPTION:

The

LP-Stack™

series is a family of interchangeable memory

devices. The 256 Megabit Double Data Rate Synchronous

DRAM is a member of this family which utilizes the new and

innovative space saving TSOP stacking technology. The

devices are constructed with two 16 Meg x 8 DDR SDRAM’

The 256 Megabit

LP-Stack™

modules DPDD16MX16TSBY5,

based on 128 Megabit devices, has been designed to fit in the

same footprint as the 16 Meg x 8 DDR SDRAM TSOP

monolithic. This allows for system upgrade without electrical or

mechanical redesign. Providing an immediate and low cost

memory solution.

PIN-OUT DIAGRAM

FEATURES:

•

Configurations Available:

16 Meg x 16 (2 Banks of 4 Meg x 8 bits x 4)

•

Clock Frequencies:

100, 125, 133, 143 MHz

•

2.5 Volt DQ Supply

•

JEDEC Standard SSTL_2 Interface for all Inputs/Outputs

•

Four Bank Operation

•

Programmable Burst Type:

Burst Length and Read Latency

•

Refresh:

4096 Cycles/64ms

•

Refresh Types:

Auto and Self

•

JEDEC Approved Footprint and Pinout

•

Package:

66-Pin Leadless TSOP Stack

PIN NAMES

A0 - A11

BA0,BA1

A10 / AP

DQ0 - DQ15

CAS

RAS

CK, CK

CKE0, CKE1

DQS0, DQS1

DM0, DM1

DDQ

SSQ

REF

N.C.

Row Address: A0 - A11

Column Address: A0 - A9

Bank Select Address

Auto Precharge

Data In / Data Out

Column Address Strobe

Chip Select

Row Address Strobe

Data Write Enable

Differential Clock Inputs

Clock Enables

Data Strobes

Data Masks

Power Supply (+2.5V)

Ground

DQ Power Supply (+2.5V)

DQ Ground

Reference Voltage for Inputs

No Connect

Not Used

FUNCTIONAL BLOCK DIAGRAM

30A245-00

REV. A

This document contains information on a product under consideration for development at Dense-Pac Microsystems, Inc.

Dense-Pac reserves the right to change or discontinue information on this product without prior notice.

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