PCD3316
Caller-ID on Call Waiting (CIDCW) receiver
11 March 1999
Product specification
1. General description
The PCD3316 is a low power mixed signal CMOS integrated circuit for receiving
physical layer signals like Bellcore’s ‘CPE
1
Alerting Signal (CAS)’ and the signals
used in similar services. The device is capable of a very high precision detection of
the dual tone (2130 and 2750 Hz) by using a patented digital algorithm. The
PCD3316 can be used for on-hook and off-hook Caller-ID (CID), Caller-ID on Call
Waiting (CIDCW) and Caller-Name (CNAM) applications.
For timing purposes the PCD3316 can be programmed to generate an interrupt
signal to the microcontroller every second or every minute. These timings are derived
from an on-chip 32.768 kHz oscillator.
Also incorporated in the device are a Frequency Shift Keying (FSK)
receiver/demodulator and a ‘Ring or polarity change detector’. The status of the
PCD3316, the received FSK data bytes and the ringer period can be read and many
options can be selected via the I
2
C-bus serial interface. Two on-chip oscillators are
available. One 3.58 MHz oscillator for all internal functions and a low frequency
32.768 kHz oscillator for the 1 second or 1 minute timing.
In Power-down mode only the polarity comparators and the 32.768 kHz oscillator are
active. The CAS detection, the FSK receiver and the 3.58 MHz oscillator can be
enabled separately. Detection of a polarity change on the inputs POL0 or POL1, the
reception of an FSK data byte, the detection of a CAS tone or a timebase interrupt is
signalled to the microcontroller by an interrupt request signal (IRQ). The
microcontroller can communicate with the PCD3316 device via the serial interface.
The PCD3316 is designed for use in a microcontroller controlled system. The device
is available in a SO16 package.
A demonstration board OM5843 and an application note
AN98071
are available.
U
c
c
nr
1.
CPE = Customer Premises Equipment.
e
ct
tri
es
d
Philips Semiconductors
PCD3316
CIDCW receiver
2. Features
s
Bellcore’s ‘CPE Alerting Signal (CAS)’ and British Telecom’s (BT) ‘Loop State
Tone Alert Signal’ detection
s
BT’s ‘Idle State Tone Alert Signal’ by means of monitoring the input signal level
s
1200 baud FSK demodulator conform Bell 202 and CCITT V23 standards
s
Ring or polarity change detector
s
Ring period measurement
s
Low battery comparator
s
Signal level detector
s
On-hook and off-hook applications according to
Bellcore TR-NWT-000030
and
SR-TSV-002476
specifications
s
Receive sensitivity of
−37.8
dBm (in 600
Ω)
for CAS
s
2.5 to 3.6 V supply; low power standby mode
s
Selectable 1 second or 1 minute timebase interrupt
s
3.58 MHz and 32.768 kHz crystal oscillators
s
SO16 package.
3. Applications
4. Ordering information
Table 1:
Ordering information
Package
Name
PCD3316T
SO16
Description
plastic small outline package; 16 leads; body width 7.5 mm
Version
SOT162-1
Type number
9397 750 04824
Product specification
U
ed
ct
tri
es
nr
s
Analog Display Services Interface (ADSI) phones
s
Feature phones and adjunct boxes with Bellcore CID, CIDCW and CNAM systems
s
Computer Telephony Integrated (CTI) systems.
© Philips Electronics N.V. 1999. All rights reserved.
11 March 1999
2 of 30
Philips Semiconductors
PCD3316
CIDCW receiver
5. Block diagram
VDD
handbook, full pagewidth
Fig 1. Block diagram.
6. Pinning information
6.1 Pinning
handbook, halfpage
Fig 2. Pin configuration.
9397 750 04824
Product specification
U
16
FSKIN+
FSKIN−
CASIN
15
14
13
PREPROCESSOR
ed
ct
tri
es
nr
HXIN
1
2
HXOUT
3.58 MHz
OSCILLATOR
TIMING
LOWBAT
POL0
POL1
12
11
10
VOLTAGE
REFERENCE
8
DGND
HXIN 1
HXOUT 2
IRQ 3
SCL 4
SDA 5
LXIN 6
LXOUT 7
DGND 8
LEVEL
DETECT
CAS
FSK
CONTROL
3
IRQ
4
I
2
C-BUS
INTERFACE
5
POR
SCL
SDA
PCD3316
6
TIME
BASE
9
MBH983
32.768 kHz
OSCILLATOR
LXIN
LXOUT
7
AGND
16 VDD
15 FSKIN+
14 FSKIN−
13 CASIN
PCD3316
12 LOWBAT
11 POL0
10 POL1
9 AGND
MBH980
© Philips Electronics N.V. 1999. All rights reserved.
11 March 1999
3 of 30
Philips Semiconductors
PCD3316
CIDCW receiver
6.2 Pin description
Table 2:
Symbol
HXIN
HXOUT
IRQ
SCL
Pin description
Pin
1
2
3
4
I/O
I
O
O
I
Description
3.58 MHz crystal oscillator input
3.58 MHz crystal oscillator output
interrupt output; programmable active HIGH or active LOW
serial clock line of I
2
C-bus
32.768 kHz crystal oscillator input
32.768 kHz crystal oscillator output
digital ground
analog ground
polarity detector input 1
polarity detector input 0
low battery detector input
input pin for CAS signal
7. Functional description
7.1 Preprocessor and analog inputs
The preprocessor for the CAS detection and the FSK receiver incorporates an
Analog-to-Digital Converter (ADC) and a digital bandpass filter.
The LOWBAT input of the PCD3316 can be used for low battery detection. The
voltage on the LOWBAT pin is compared with an internal voltage reference circuit.
When the LOWBAT voltage drops below the reference voltage, the Status register,
bit 5 is set to logic 1.
The PCD3316 can be forced in a Power-down state by switching off the 3.58 MHz
system clock and the ADC. This is done by setting Mode register 2, bit 7 (CIDMD2.7)
to logic 0. To guarantee correct operation the following order of actions must be
performed (see also
Section 7.8
about interrupts):
1. Switch off CAS and FSK detection (if turned on)
2. Read the interrupt register (thus clearing pending interrupts generated by the
CAS and FSK detector)
3. Switch off the 3.58 MHz oscillator by clearing bit 7 of Mode register 2.
The two low power comparators (inputs POL0 and POL1) and the 32.768 kHz clock
are always active.
9397 750 04824
Product specification
U
ed
ct
tri
es
nr
SDA
5
I/O
I
O
−
−
I
I
I
I
LXIN
6
7
8
LXOUT
DGND
AGND
POL1
POL0
9
10
11
12
LOWBAT
CASIN
FSKIN−
13
14
15
I
FSKIN+
V
DD
I
16
−
serial data line of I
2
C-bus
negative input for FSK signal
supply
positive input for FSK signal
© Philips Electronics N.V. 1999. All rights reserved.
11 March 1999
4 of 30
Philips Semiconductors
PCD3316
CIDCW receiver
They can be used for ring or line polarity reversal detection. The POL on/off bit (Mode
register 1, bit 4) must be set to enable generation of an interrupt when a polarity
change occurs. The result of the two comparators can be read in bits 7 and 6 (POL0
and POL1) of the Status register (see
Section 7.4).
The 3.58 MHz clock is not needed
for the generation of a polarity interrupt.
9397 750 04824
Product specification
U
7.2 CAS detection
ed
ct
tri
es
nr
7.3 FSK reception
width
After a power-on reset or after enabling the CAS detector the internal registers of the
CAS detection function are initialized. The initialization takes a maximum of
100 periods of the 3.58 MHz clock.
If the CAS detection is enabled the PCD3316 will generate an interrupt (Interrupt
register, bit 1 is set) when a correct dual tone (2130 and 2750 Hz) is detected.
Interrupts will be blocked when the signal level on the CAS input is below the
threshold in the level detector.
The FSK receiver function can be enabled by setting the FSK on/off bit (Mode
register 1, bit 7).
In the FSK transmission specification of BT and Bellcore a channel seizure is
transmitted first (sequence of 1010..). After the channel seizure a block of marks and
finally the data pattern are sent (see
Figure 3).
These mark bits are detected by the
PCD3316 which sets the FSK-BOM Indication bit (Status register, bit 4). The
FSK-BOM Indication bit is reset when the FSK receiver is disabled.
FSK transmission
channel seizure
mark
data
FSK-BOM
MBH979
Fig 3. FSK transmission specification.
If the FSK-BOM Indication bit is set, the FSK receiver will generate an interrupt after it
has received a complete data word. An FSK data word consists of one start bit
(space), followed by eight data bits and one stop bit (mark). Interrupts will therefore
not be generated during the channel seizure and during the block of marks. When a
valid data word has been received, FSK data is available in the FSK data register.
By clearing the FSK-BOM-mask on/off bit (Mode register 1, bit 6), the FSK receiver
will not wait with the generation of interrupts until a Begin Of Mark (BOM) has been
detected but will handle the channel seizure as normal data. The block of marks
which is a string of logic 1 will still not generate interrupts because there are no start
bits.
After the generation of an interrupt the IRQ pin will become active (see
Figure 4),
and
the FSK Interrupt bit is set (Interrupt register, bit 5). The received data is available in
the FSK data register.
© Philips Electronics N.V. 1999. All rights reserved.
11 March 1999
5 of 30
京公网安备 11010802033920号
EEWORLD
