Input from fundamental crystal oscillator or external source
Balanced Drive Outputs ±12mA
PLL disable mode for low frequency testing
Select inputs (S
[1:0]
) for divide selection (multiply ratio of 2,
3, 4, 5, 6, 7, and 8)
5V tolerant inputs
Low output skew/jitter
External PLL feedback, internal loop filter
Available in 16-pin QSOP package
APPLICATIONS:
•
•
•
•
•
Ethernet/fast ethernet
Router
Network switches
SAN
Instrumentation
The IDT5V925 is a high-performance, low skew, low jitter phase-locked
loop (PLL) clock driver. It provides precise phase and frequency alignment
of its clock outputs to an externally applied clock input or internal crystal
oscillator. The IDT5V925 has been specially designed to interface with
Gigabit Ethernet and Fast Ethernet applications by providing a 125MHz
clock from 25MHz input. It can also be programmed to provide output
frequencies ranging from 3.125MHz to 160MHz with input frequencies
ranging from 3.125MHz to 80MHz.
The IDT5V925 includes an internal RC filter that provides excellent jitter
characteristics and eliminates the need for external components. When
using the optional crystal input, the chip accepts a 10-30MHz fundamental
mode crystal with a maximum equivalent series resistance of 50Ω. The on-
chip crystal oscillator includes the feedback resistor and crystal capacitors
(nominal load capacitance is 15pF).
FUNCTIONAL BLOCK DIAGRAM
S
0
S
1
SE LEC T
M OD E
FB
C LKIN
PH ASE
DETEC TO R
LOO P
FILTER
VC O
0
1
VC O
DIVIDE
1/N
Q /N
X
2
X
1
OPTION AL
C RYSTAL
XTAL
OSC
Q
0
Q
1
Q
2
OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2004 Integrated Device Technology, Inc.
SEPTEMBER 2002
DSC-5943/2
IDT5V925
PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Description
Supply Voltage to Ground
DC Output Voltage V
OUT
DC Input Voltage V
IN
T
A
= 85°C
T
STG
Maximum Power Dissipation
Storage Temperature
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–0.5 to +7
.55
–65 to +150
Unit
V
V
V
W
°C
S
1
S
0
GNDQ
V
DDQ
X
1
X
2
CLKIN
FB
1
2
3
4
5
6
7
8
QSOP
TOP VIEW
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
V
DD
GND
Q
2
Q
1
Q
0
Q/N
GND
OE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Names
CLKIN
X
1
(1)
I/O
I
I
O
I
Description
Input clock
Crystal oscillator input. Connected to GND if
oscillator not required.
Crystal oscillator output. Leave unconnected for
clock input.
PLL feedback input which should be connected to
Q/N output pin only. PLL locks onto positive edge
of FB signal.
Three level divider/mode select pins. Float to MID.
Output at N*CLKIN frequency
Programmable divide-by-N clock output
Tri-state output enable. When asserted HIGH, clock
outputs are high impedance.
Power supply for output buffers
Ground supply for output buffers
Power supply for PLL
Ground supply for PLL
CRYSTAL SPECIFICATION
The crystal oscillators should be fundamental mode quartz crystals:
overtone crystals are not suitable. Crystal frequency should be specified
for parallel resonance with 50Ω maximum equivalent series resonance.
X
2
(1)
FB
S
[1:0]
Q
[2:0]
Q/N
OE
V
DD
GND
V
DDQ
GNDQ
I
O
O
I
PWR
PWR
PWR
PWR
FUNCTION TABLE
Output Used for
Feedback
Q/N
Allowable CLKIN Range (MHz)
(1,2)
Minimum
25/N
Maximum
160/N
NOTE:
1. For best accuracy, use parallel resonant crystal specified for a load capacitance
of 15pF.
Output Frequency Relationships
Q/N
CLKIN
Q
[2:0]
CLKIN x N
NOTES:
1. Operation in the specified CLKIN frequency range guarantees that the VCO will operate in the optimal range of 25MHz to 160MHz. Operation with CLKIN outside specified
frequency ranges may result in invalid or out-of-lock outputs.
2. Q
[2:0
] is not allowed to be used as feedback.
2
IDT5V925
PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
DIVIDE SELECTION TABLE
(1)
S1
L
L
L
M
M
M
H
H
H
S0
L
M
H
L
M
H
L
M
H
2
3
4
5
(3)
6
7
8
16
Divide-by-N Value
FACTORY TEST
(2)
PLL
PLL
PLL
PLL
PLL
PLL
PLL
TEST
(4)
Mode
NOTES:
1. H = HIGH
M = MEDIUM
L = LOW
2. Factory Test Mode: operation not specified,
3. Ethernet mode (use a 25MHz input frequency and Q/N as feedback).
4. Test mode for low frequency testing. In this mode, CLKIN bypasses the VCO (VCO powered down). Frequency must be > 1MHz due to dynamic circuits in the frequency
dividers. Q
[2:0]
outputs are divided by 2 in test mode.
OPERATING CONDITIONS
Symbol
V
DD/
V
DDQ
T
A
C
L
C
IN
Description
Power Supply Voltage
Operating Temperature
Output Load Capacitance
Input Capacitance, CLKIN, FB,
OE,
F = 1MHz, V
IN
= 0V, T
A
= 25°C
Min.
3
–40
—
—
Typ.
3.3
+25
—
5
Max.
3.6
+85
15
7
Unit
V
°C
pF
pF
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 3.3V ±0.3V
Symbol
V
IL
V
IH
V
IHH
(1)
V
IMM
(1)
V
ILL
(1)
I
IN
Parameter
Input LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Input MID Voltage
Input LOW Voltage
Input Leakage Current
(CLKIN, FB Inputs only)
3-Level Input DC Current, S
[1:0]
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Test Conditions
Min.
—
2
V
DD
- 0.6
V
DD
/2 - 0.3
—
-5
—
- 50
- 200
-5
—
2.4
Typ.
(7)
—
—
—
—
—
—
—
—
—
0.07
0.15
2.8
Max
0.8
—
—
V
DD
/2 + 0.3
0.6
+5
+200
+50
—
+5
0.55
—
Unit
V
V
V
V
V
µA
3-level input only
3-level input only
3-level input only
V
IN
= V
DD
or GND, V
DD
= Max
V
IN
= V
DD
V
IN
= V
DD
/2
V
IN
= GND
V
IN
= V
DD
I
OL
= 12mA
I
OH
= -12mA
HIGH Level
MID Level
LOW Level
I
3
I
IH
V
OL
V
OH
µA
µA
V
V
NOTE:
1. These inputs are normally wired to V
CC
, GND, or unconnected. If the inputs are switched in real time, the function and timing of the outputs may glitch, and the PLL may require
an additional lock time before all the datasheet limits are achieved.
3
IDT5V925
PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
I
DDQ
Parameter
Quiescent Supply Current
Test Conditions
(1)
V
DD
= Max.
CLKIN = FB = X
1
= GND
S
[1:0]
= HH
OE
= H
All outputs unloaded
∆I
DD
I
DD
Supply Current per Input
Dynamic Supply Current
V
DD
= Max., V
IN
= 3V
V
DD
= 3.6V
S
[1:0]
=LM
OE
= GND
F
OUT
= 60MHz
All outputs unloaded
NOTE:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
Min.
—
Typ.
0.7
Max
2
Unit
mA
—
—
1
77
30
130
µA
mA
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 3.3V ±0.3V
Symbol
t
R,
t
F
d
T
t
PD
t
SK
t
J
f
OUT
Parameter
Rise Time, Fall Time
(1)
Output/Duty Cycle
(1)
CLKIN to FB
(1)
Output to Output Skew
(1)
Cycle - Cycle Jitter
(1)
Output Frequency
Test Conditions
0.8V to 2V
V
T
= V
DD
/2
V
T
= V
DD
/2
V
T
= V
DD
/2; Q
[2:0]
V
T
= V
DD
/2; Q/N - Q
[2:0]
Min.
—
45
- 300
—
—
—
25
Typ.
0.7
—
—
—
—
—
—
Max.
1.5
55
300
100
300
200
160
ps
MHz
Unit
ns
%
ps
ps
NOTE:
1. This parameter is guaranteed by design but not tested.
INPUT TIMING REQUIREMENTS
Symbol
t
R,
t
F
D
H
f
OSC
f
IN
Description
Maximum Input Rise and Fall Time, 0.8V to 2V
Input Duty Cycle
(1)
XTAL Oscillator Frequency
Input Frequency
(1)
Min.
—
25
—
25/N
Max.
2
75
30
160/N
Unit
ns
%
MHz
MHz
NOTE:
1. This parameter is guaranteed by design but not tested.
4
IDT5V925
PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
TEST LOADS AND WAVEFORMS
3V
V
CC
2V
V
T H
= V
C C
/2
150
Ω
0.8
0V
OUTPUT
1ns
1ns
Input Test Waveform
15pF
150
Ω
V
C C
2V
AC Test Load
V
T H
= V
C C
/2
0.8
0V
t
R
t
F
Output Waveform
HOW TO USE THE 5V925
The 5V925 is a general-purpose phase-locked loop (PLL) that can be
used as a zero delay buffer or a clock multiplier. It generates three outputs
at the VCO frequency and one output at the VCO frequency divided by n,
where n is determined by the Mode/Frequency Select input pins S
0
and S
1
.
The PLL will adjust the VCO frequency (within the limits of the Function
Table) to ensure that the input frequency equals the Q/N frequency.
The 5V925 can accept two types of input signal. The first is a reference
clock generated by another device on the board which needs to be
reproduced with a minimal delay between the incoming clock and output.
The second is an external crystal. When used in the first mode, the crystal
input (X
1
) should be tied to ground and the crystal output (X
2
) should be left
unconnected.
By connecting Q/N to FB (see Figure 1), the 5V925 not only becomes
a zero delay buffer, but also a clock multiplier. With proper selection of S
0
and S
1
, the Q
0
–Q
2
outputs will generate two, three, up to eight times the input
clock frequency. Make sure that the input and output frequency specifica-
tions are not violated (refer to Function Table). There are some applications
where higher fan-out is required. These kinds of applications could be
addressed by using the 5V925 in conjunction with a clock buffer such as the
49FCT3805. Figure 2 shows how higher fan-out with different clock rates
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