Data Sheet No. PD60213 revC
IR2114SS/ IR21141SS
IR2214SS/IR22141SS
HALF-BRIDGE GATE DRIVER IC
Features
•
•
•
•
•
•
•
•
Floating channel up to +600 or +1200V
Soft over-current shutdown
Synchronization signal to synchronize shut down with the other phases
Integrated desaturation detection circuit
Two stage turn on output for di/dt control
Separate pull-up/pull-down output drive pins
Matched delay outputs
Under voltage lockout with hysteresis band
Product Summary
V
OFFSET
IO+/- (typ)
V
OUT
Deadtime matching (max)
Deadtime (typ)
Desat blanking time (typ)
DSH, DSL input voltage
threshold (typ)
Soft shutdown time (typ)
600V or
1200V max.
2.0 A / 3.0A
10.4V - 20V
75 nsec
330
nsec
3
µsec
8.0 V
9.25
µsec
Description
The IR2114/21141/2214/IR22141 gate driver family is suited to drive a single
half bridge in power switching applications. The high gate driving capability (2A
source, 3A sink) and the low quiescent current enable bootstrap supply
techniques in medium power systems. These drivers feature full short circuit
protection by means of the power transistor desaturation detection and manages
all the half-bridge faults by turning off smoothly the desaturated transistor
through the dedicated soft shut down pin, therefore preventing over-voltages and
reducing EM emissions. In multi-phase system IR2114/21141/2214/IR22141
drivers communicate using a dedicated local network (SY_FLT and FAULT/SD
signals) to properly manage phase-to-phase short circuits. The system controller
may force shutdown or read device fault state through the 3.3 V compatible
CMOS I/O pin (FAULT/SD). To improve the signal immunity from DC-bus noise,
the control and power ground use dedicated pins enabling low-side emitter
current sensing as well. Undervoltage conditions in floating and low voltage
circuits are managed independently.
Package
24-Lead SSOP
Typical connection
DC+
15 V
VCC
VB
HOP
HON
SSDH
LIN
DC BUS
(1200V)
IR2214
HIN
uP,
Control
FAULT/SD
FLT_CLR
SY_FLT
DSH
VS
Motor
LOP
LON
SSDL
DSL
VSS
COM
DC-
1
IR2114/IR21141/IR2214/IR22141
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to V
SS
, all currents are defined positive into any lead
The thermal resistance and power dissipation ratings are measured under board mounted and still air
conditions.
Symbol
V
S
V
B
V
HO
V
CC
COM
V
LO
V
IN
V
FLT
V
DSH
V
DSL
dVs/dt
P
D
Rth
JA
T
J
T
S
T
L
Definition
High side offset voltage
High side floating supply voltage
Min.
Max.
V
B
+ 0.3
625
1225
V
B
+ 0.3
25
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
V
B
+ 0.3
V
CC
+ 0.3
50
1.5
65
125
150
300
Units
V
B
- 25
-0.3
(IR2114 or IR21141)
-0.3
(IR2214 or IR22141)
High side floating output voltage (HOP, HON and SSDH) V
S
- 0.3
Low side and logic fixed supply voltage
-0.3
Power ground
V
CC
- 25
Low side output voltage (LOP, LON and SSDL)
V
COM
-0.3
Logic input voltage (HIN, LIN and FLT_CLR)
V
SS
-0.3
FAULT input/output voltage (FAULT/SD and SY_FLT)
V
SS
-0.3
High side DS input voltage
V
S
-3
Low side DS input voltage
V
COM
-3
Allowable offset voltage slew rate
—
Package power dissipation @ TA
≤
+25°C
—
Thermal resistance, junction to ambient
—
Junction temperature
—
Storage temperature
-55
Lead temperature (soldering, 10 seconds)
—
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters
are absolute voltages referenced to V
SS
. The V
S
offset rating is tested with all supplies biased at 15V
differential.
Symbol
V
B
V
S
Definition
High side floating supply voltage (Note 1)
High side floating supply offset
(IR2114 or IR21141)
voltage
(IR2214 or IR22141)
Min.
Max.
Units
V
S
+ 11.5
V
S
+ 20
Note 2
600
Note 2
1200
V
HO
High side output voltage (HOP, HON and SSDH)
V
S
V
S
+ 20
V
LO
Low side output voltage (LOP, LON and SSDL)
V
COM
V
CC
V
V
CC
Low side and logic fixed supply voltage (Note 1)
11.5
20
COM
Power ground
-5
5
V
IN
Logic input voltage (HIN, LIN and FLT_CLR)
V
SS
V
CC
V
FLT
Fault input/output voltage (FAULT/SD and SY_FLT)
V
SS
V
CC
V
DSH
High side DS pin input voltage
V
S
- 2.0
V
B
V
DSL
Low side DS pin input voltage
V
COM
- 2.0
V
CC
T
A
Ambient temperature
-40
125
°C
Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables
the output drivers if the UV thresholds are not reached.
Note 2: Logic operational for V
S
from V
SS
-5V to V
SS
+600V or 1200V. Logic state held for V
S
from V
SS
-5V to
V
SS
-V
BS
. (Please refer to the Design Tip DT97-3 for more details).
2
IR2114/IR21141/IR2214/IR22141
Static Electrical Characteristics
V
CC
= 15 V, V
SS
= COM = 0 V, V
S
= 0 ÷ 600V or 1200 V and T
A
= 25 °C unless otherwise specified.
Pin: V
CC
, V
SS
, V
B
, V
S
Symbol
V
CCUV+
V
CCUV-
V
CCUVH
V
BSUV+
V
BSUV-
V
BSUVH
I
LK
I
QBS
I
QCC
Definition
Vcc supply undervoltage positive going threshold
Vcc supply undervoltage negative going threshold
Vcc supply undervoltage lockout hysteresis
(V
B
-V
S
) supply undervoltage positive going threshold
(V
B
-V
S
) supply undervoltage negative going
threshold
(V
B
-V
S
) supply undervoltage lockout hysteresis
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent Vcc supply current
comparator
V
CC
/V
B
UV
internal
signal
Min Typ Max Units Test Conditions
9.3 10.2 11.4
8.7 9.3 10.3
-
0.9
-
9.3 10.2 11.4 V
V
S
=0V, V
S
=600V
or 1200V
8.7 9.3 10.3
V
S
=0V, V
S
=600V
or 1200V
-
0.9
-
-
-
50
V
B
= V
S
= 600V or
1200V
µA
-
400 800
V
IN
= 0V or 3.3V
-
0.7 2.5 mA
(No load)
V
CCUV
/V
BSUV
V
SS
/V
S
Figure 1:
Undervoltage diagram
Pin: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT
Symbol
V
IH
V
IL
Definition
Logic "1" input voltage
Logic "0" input voltage
Logic input hysteresis
Logic "1" input bias current
Logic "0" input bias current
FAULT/SD open drain resistance
SY_FLT open drain resistance
schmitt
trigger
HIN/LIN/
FLTCLR
10k
internal
signal
V
IHSS
I
IN+
I
IN-
R
ON,FLT
R
ON,SY
Min
2.0
-
0.2
-
-1
-
-
Typ
-
-
0.4
370
-
60
60
Max Units Test Conditions
-
V
CC
= V
CCUV-
to
V
0.8
20V
-
-
0
-
-
µA
Ω
V
IN
= 3.3V
V
IN
= 0V
PW
≤
7
µs
V
SS
Figure 2:
HIN, LIN and FLTCLR diagram
3
IR2114/IR21141/IR2214/IR22141
FAULT/SD
SY_FLT
fault/hold
internal signal
schmitt
trigger
R
ON
hard/soft shutdown
internal signal
V
SS
Figure 3:
FAULT/SD and SY_FLT diagram
Pin: DSL, DSH
The active bias is present only in IR21141 and IR22141. V
DESAT
, I
DS
and I
DSB
parameters are referenced to
COM and V
S
respectively for DSL and DSH.
Symbol
Definition
Min Typ Max Units
Test Conditions
V
DESAT+
V
DESAT-
V
DSTH
I
DS+
I
DS-
I
DSB
High desat input threshold voltage
Low desat input threshold voltage
Desat input voltage hysteresis
High DSH or DSL input bias current
Low DSH or DSL input bias current
DSH or DSL input bias current
(IR21141 and IR22141 only)
V
CC
/V
BS
7.2 8.0 8.8
6.3 7.0 7.7
-
1.0
-
-
21
-
- -160 -
-
-20
-
V
µA
mA
See Fig. 16, 4
V
DESAT
= V
CC
or V
BS
V
DESAT
= 0V
V
DESAT
=
(V
CC
or V
BS
) - 2V
100k
active
bias
comparator
DSL/DSH
V
DESAT
SSD
700k
internal
signal
COM/V
S
Figure 4:
DSH and DSL diagram.
4
IR2114/IR21141/IR2214/IR22141
Pin: HOP, LOP
Symbol
V
OH
I
O1+
Definition
High level output voltage, V
B
– V
HOP or
V
cc
–V
LOP
Output high first stage short circuit pulsed current
Min Typ Max Units Test Conditions
I
O
= 20mA
-
40 300 mV
-
2
-
V
HOP/LOP
=0V,
H
IN
or L
IN
= 1,
PW≤200ns,
resistive load,
see Fig. 8
A
-
1
-
V
HOP/LOP
=0V,
H
IN
or L
IN
= 1,
400ns≤PW≤10µs,
resistive load,
see Fig. 8
I
O2+
Output high second stage short circuit pulsed current
200ns
oneshot
V
CC
/V
B
V
OH
on/off
internal signal
LOP/HOP
Figure 5:
HOP and LOP diagram
Pin: HON, LON, SSDH, SSDL
Symbol
V
OL
R
ON,SSD
I
O-
Definition
Low level output voltage, V
HON or
V
LON
Soft Shutdown on resistance (Note 1)
Output low short circuit pulsed current
Min Typ Max Units Test Conditions
I
O
= 20mA
-
45 300 mV
Ω
-
90
-
PW
≤
7
µs
-
3
-
A
V
HOP/LOP
=15V,
H
IN
or L
IN
= 0,
PW≤10µs
Note 1: SSD operation only.
LON/HON
on/off
internal signal
desat
internal signal
SSDL/SSDH
V
OL
R
ON,SSD
COM/V
S
Figure 6:
HON, LON, SSDH and SSDL diagram
5
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