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IDT70P35L25BYI

Description
HIGH-SPEED 1.8V 8/4K x 18 DUAL-PORT, 8/4K x 16 DUAL-PORT STATIC RAM
File Size294KB,22 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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IDT70P35L25BYI Overview

HIGH-SPEED 1.8V 8/4K x 18 DUAL-PORT, 8/4K x 16 DUAL-PORT STATIC RAM

HIGH-SPEED 1.8V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
Features
ADVANCED
IDT70P35/34L
IDT70P25/24L
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
IDT70P35/34L (IDT70P25/24L)
– Commercial: 20/25ns (max.)
– Industrial: 25ns (max.)
Low-power operation
IDT70P35/34L (IDT70P25/24L)
Active: 30.6mW (typ.)
Standby: 5.4mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70P35/34L (IDT70P25/24L) easily expands data bus
width to 36 bits (32 bits) or more using the Master/Slave
select when cascading more than one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 1.8V (±100mV) power supply
Available in a 100-pin Thin Quad Flatpack (TQFP) package,
100-pin 0.8mm pitch Ball Grid Array (fpBGA), and 100-pin
0.5mm pitch BGA (fpBGA)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/W
L
UB
L
R/W
R
UB
R
LB
CE
L
L
OE
L
LB
R
CE
R
OE
R
,
I/O
9L
-I/O
17L
(5)
I/O
0L
-I/O
8L
(4)
BUSY
L
A
12L
(1)
A
0L
(2,3)
I/O
9R
-I/O
17R
(5)
I/O
Control
I/O
Control
I/O
0R
-I/O
8R
(4)
BUSY
R
(2,3)
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
A
12R
(1)
A
0R
CE
L
OE
L
R/W
L
SEM
L
(3)
INT
L
NOTES:
1. A
12
is a NC for IDT70P34 and IDT70P24.
2. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
3.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
4. I/O
0
x - I/O
7
x for IDT70P25/24.
5. I/O
8
x - I/O
15
x for IDT70P25/24.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(3)
5683 drw 01
M/S
FEBRUARY 2004
1
DSC-5683/2
©2004 Integrated Device Technology, Inc.
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