82V32021NL datasheet, PDF - EEWORLD Datasheet

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82V32021NL: DescriptionPLL Based Clock Driver, 5V Series, 1 True Output(s), 0 Inverted Output(s), PLASTIC, VFQFPN-68; Categorylogic logic; File Size1MB，108 Pages; ManufacturerIDT (Integrated Device Technology)

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82V32021NL Overview

PLL Based Clock Driver, 5V Series, 1 True Output(s), 0 Inverted Output(s), PLASTIC, VFQFPN-68

82V32021NL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFN
package instruction	PLASTIC, VFQFPN-68
Contacts	68
Manufacturer packaging code	VFQFPN
Reach Compliance Code	not_compliant
series	5V
Input adjustment	MUX
JESD-30 code	S-XQCC-N68
JESD-609 code	e0
length	10 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	68
Actual output times	1
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	10 mm
Base Number Matches	1

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EBU WAN PLL

IDT82V32021

Version 3

July 23, 2009

6024 Silver Creek Valley Road, San Jose, CA 95138

Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775

Printed in U.S.A.

Table of Contents

FEATURES .............................................................................................................................................................................. 8

HIGHLIGHTS.................................................................................................................................................................................................... 8

MAIN FEATURES ............................................................................................................................................................................................ 8

OTHER FEATURES ......................................................................................................................................................................................... 8

APPLICATIONS....................................................................................................................................................................... 8

DESCRIPTION......................................................................................................................................................................... 9

FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 10

1 PIN ASSIGNMENT ........................................................................................................................................................... 11

2 PIN DESCRIPTION .......................................................................................................................................................... 12

3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 16

3.1

3.2

3.3

RESET ........................................................................................................................................................................................................... 16

MASTER CLOCK .......................................................................................................................................................................................... 16

INPUT CLOCKS & FRAME SYNC SIGNALS ............................................................................................................................................... 17

3.3.1 Input Clocks .................................................................................................................................................................................... 17

3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 17

3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 18

3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 19

3.5.1 Activity Monitoring ......................................................................................................................................................................... 19

3.5.2 Frequency Monitoring ................................................................................................................................................................... 20

3.6 DPLL INPUT CLOCK SELECTION .............................................................................................................................................................. 21

3.6.1 External Fast Selection .................................................................................................................................................................. 21

3.6.2 Forced Selection ............................................................................................................................................................................ 22

3.6.3 Automatic Selection ....................................................................................................................................................................... 22

3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 23

3.7.1 DPLL Locking Detection ................................................................................................................................................................ 23

3.7.1.1 Fast Loss .......................................................................................................................................................................... 23

3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 23

3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 23

3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 23

3.7.2 Locking Status ............................................................................................................................................................................... 23

3.7.3 Phase Lock Alarm .......................................................................................................................................................................... 23

3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 25

3.8.1 Input Clock Validity ........................................................................................................................................................................ 25

3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 25

3.8.2.1 Revertive Switch ............................................................................................................................................................... 25

3.8.2.2 Non-Revertive Switch ....................................................................................................................................................... 25

3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 25

3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 27

3.10 DPLL OPERATING MODE ........................................................................................................................................................................... 29

3.10.1 Six Operating Modes ..................................................................................................................................................................... 29

3.10.1.1 Free-Run Mode ................................................................................................................................................................ 29

3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 29

3.10.1.3 Locked Mode .................................................................................................................................................................... 29

3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 29

3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 29

3.10.1.5 Holdover Mode ................................................................................................................................................................. 29

Table of Contents

July 23, 2009

IDT82V32021

EBU WAN PLL

3.11

3.12

3.13

3.14

3.15

3.16

4.1

3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 30

3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 30

3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 30

3.10.1.5.4 Manual ........................................................................................................................................................... 30

3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 30

3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 30

DPLL OUTPUT .............................................................................................................................................................................................. 32

3.11.1 PFD Output Limit ............................................................................................................................................................................ 32

3.11.2 Frequency Offset Limit .................................................................................................................................................................. 32

3.11.3 PBO ................................................................................................................................................................................................. 32

3.11.4 Four Paths of T0 DPLL Output ...................................................................................................................................................... 32

T0 APLL ........................................................................................................................................................................................................ 34

OUTPUT CLOCK & FRAME SYNC SIGNALS ............................................................................................................................................. 34

3.13.1 Output Clock ................................................................................................................................................................................... 34

3.13.2 Frame SYNC Output Signal ........................................................................................................................................................... 36

INTERRUPT SUMMARY ............................................................................................................................................................................... 38

T0 SUMMARY ............................................................................................................................................................................................... 38

LINE CARD APPLICATION .......................................................................................................................................................................... 39

FUNCTION DESCRIPTION ........................................................................................................................................................................... 40

4.1.1 Data Transfer Format ..................................................................................................................................................................... 41

4.1.1.1 Slave-receiver Mode (Write) ............................................................................................................................................. 41

4.1.1.2 Slave-transmitter Mode (Read) ........................................................................................................................................ 41

4.1.2 Address Assignment ..................................................................................................................................................................... 42

TIMING DEFINITION ..................................................................................................................................................................................... 42

4 I2C PROGRAMMING INTERFACE .................................................................................................................................. 40

5 JTAG ................................................................................................................................................................................ 44

6 PROGRAMMING INFORMATION .................................................................................................................................... 45

6.1

6.2

REGISTER MAP ............................................................................................................................................................................................ 45

REGISTER DESCRIPTION ........................................................................................................................................................................... 49

6.2.1 Global Control Registers ............................................................................................................................................................... 49

6.2.2 Interrupt Registers ......................................................................................................................................................................... 56

6.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 60

6.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 65

6.2.5 T0 DPLL Input Clock Selection Registers .................................................................................................................................... 73

6.2.6 T0 DPLL State Machine Control Registers .................................................................................................................................. 75

6.2.7 T0 DPLL & T0 APLL Configuration Registers .............................................................................................................................. 77

6.2.8 Output Configuration Registers .................................................................................................................................................... 88

6.2.9 PBO & Phase Offset Control Registers ........................................................................................................................................ 90

6.2.10 Synchronization Configuration Registers ................................................................................................................................... 91

JUNCTION TEMPERATURE ........................................................................................................................................................................ 92

EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ..................................................................................................................... 92

HEATSINK EVALUATION ............................................................................................................................................................................ 92

VFQFPN EPAD THERMAL RELEASE PATH .............................................................................................................................................. 93

ABSOLUTE MAXIMUM RATING .................................................................................................................................................................. 94

RECOMMENDED OPERATION CONDITIONS ............................................................................................................................................ 94

I/O SPECIFICATIONS ................................................................................................................................................................................... 95

8.3.1 CMOS Input / Output Port .............................................................................................................................................................. 95

JITTER & WANDER PERFORMANCE ......................................................................................................................................................... 97

OUTPUT WANDER GENERATION .............................................................................................................................................................. 99

INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 100

4.2

7 THERMAL MANAGEMENT ............................................................................................................................................. 92

7.1

7.2

7.3

7.4

8.1

8.2

8.3

8.4

8.5

8.6

8 ELECTRICAL SPECIFICATIONS .................................................................................................................................... 94

Table of Contents

July 23, 2009

82V32021NL Related Products

	82V32021NL	82V32021NL8
Description	PLL Based Clock Driver, 5V Series, 1 True Output(s), 0 Inverted Output(s), PLASTIC, VFQFPN-68	Clock Generator, PQCC68
Is it Rohs certified?	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Reach Compliance Code	not_compliant	unknown
JESD-30 code	S-XQCC-N68	S-PQCC-N68
JESD-609 code	e0	e0
Humidity sensitivity level	3	3
Number of terminals	68	68
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	UNSPECIFIED	PLASTIC/EPOXY
encapsulated code	HVQCCN	QCCN
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER
Certification status	Not Qualified	Not Qualified
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Base Number Matches	1	1

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