CY38015V144-66BBC datasheet, PDF

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CY38015V144-66BBC: DescriptionLoadable PLD, 18.9ns, CMOS, PBGA144, FBGA-144; CategoryProgrammable logic devices Programmable logic; File Size930KB，32 Pages; ManufacturerCypress Semiconductor

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CY38015V144-66BBC Overview

Loadable PLD, 18.9ns, CMOS, PBGA144, FBGA-144

CY38015V144-66BBC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	BGA,
Contacts	144
Reach Compliance Code	unknown
Other features	IT CAN ALSO HAVE AN INPUT VOLTAGE OF 3.3V
JESD-30 code	S-PBGA-B144
Dedicated input times
Number of I/O lines	92
Number of terminals	144
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 92 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	LOADABLE PLD
propagation delay	18.9 ns
Certification status	Not Qualified
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
Base Number Matches	1

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PRELIMINARY

Quantum38K™ ISR™

CPLD Family

CPLDs at ASIC Prices™

Features

• High density

— 15K to 100K usable gates

— 256 to 1536 macrocells

— 92 to 302 maximum I/O pins

— 8 Dedicated Inputs including 4 clock pins and 4

global control signal pins; 4 JTAG interface pins for

reconfigurability

• Embedded Memory

— 8K to 48K bits embedded dual-port Channel memory

• 83 MHz in-system operation

• AnyVolt™ interface

— 3.3V and 2.5V V

operation

— 3.3V, 2.5V and 1.8V I/O capability

• Low Power Operation

—

0.18-µm 6-layer metal SRAM-based logic process

— Full-CMOS implementation of product term array

• Simple timing model

— No penalty for using full 16 product terms / macrocell

— No delay for single product term steering or sharing

• Flexible clocking

— 4 synchronous clocks per device

— Locally generated Product Term clock

— Clock polarity control at each register

• Carry-chain logic for fast and efficient arithmetic oper-

ations

• Multiple I/O standards supported:

•

— LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI

Compatible with NOBL™, ZBT™, and QDR™ SRAMs

Programmable slew rate control on each I/O pin

User-Programmable Bus Hold capability on each I/O

Fully PCI compliant (as per PCI spec rev. 2.2)

Compact PCI hot swap compatible

Multiple package/pinout offering across all densities

— 144 to 484 pins in PQFP and FBGA packages

— Simplifies design migration across density

In-System Reprogrammable™ (ISR™)

— JTAG-compliant on-board configuration

— Design changes don’t cause pinout changes

• IEEE1149.1 JTAG boundary scan

Development Software

•

Warp®

— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context

sensitive editing

— Active-HDL FSM graphical finite state machine editor

— Active-HDL SIM post-synthesis timing simulator

— Architecture Explorer for detailed design analysis

— Static Timing Analyzer for critical path analysis

— Available on Windows 95, 98 & NT for $99

— Supports all Cypress Programmable Logic Products

Quantum38K™ ISR CPLD Family Members

Channel

memory

(Kbits)

Maximum

I/O Pins

134

176

218

302

MAX2

(MHz)

Speed — t

Pin-to-Pin

(ns)

Standby I

[2]

=25°C

3.3/2.5V

10 mA

Device

38K15

38K30

38K50

38K100

Typical Gates

[1]

8K–24K

16K–48K

23K–72K

46K–144K

Macrocells

256

512

768

1536

Note:

1. Upper limit of typical gates is calculated by assuming only 50% of the channel memory is used.

2. Standby I

values are with no output load and stable inputs.

Cypress Semiconductor Corporation

Document #: 38-03043 Rev. **

•

3901 North First Street

•

San Jose

•

CA 95134 • 408-943-2600

Revised April 20, 2001

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