IDT72255L20PF datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > IDT72255L20PF

Preview

IDT72255L20PF: DescriptionCMOS SUPERSYNC FIFOO 8,192 x 18, 16,384 x 18; File Size270KB，30 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

Download Datasheet View All

IDT72255L20PF Overview

CMOS SUPERSYNC FIFOO 8,192 x 18, 16,384 x 18

Preview

Download Datasheet

View All

CMOS SUPERSYNC FIFO™

8,192 x 18, 16,384 x 18

Integrated Device Technology, Inc.

IDT72255

IDT72265

FEATURES:

•

8,192 x 18-bit storage capacity (IDT72255)

16,384 x 18-bit storage capacity (IDT72265)

10ns read/write cycle time (8ns access time)

Retransmit Capability

Auto power down reduces power consumption

Master Reset clears entire FIFO, Partial Reset clears

data, but retains programmable settings

Empty, Full and Half-full flags signal FIFO status

Programmable Almost Empty and Almost Full flags, each

flag can default to one of two preselected offsets

Program partial flags by either serial or parallel means

Select IDT Standard timing (using

and

flags) or

First Word Fall Through timing (using

and

flags)

Easily expandable in depth and width

Independent read and write clocks (permit simultaneous

reading and writing with one clock signal)

Available in the 64-pin Thin Quad Flat Pack (TQFP), 64-

pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin

Pin Grid Array (PGA)

Output enable puts data outputs into high impedance

High-performance submicron CMOS technology

Industrial temperature range (-40

C to +85

C) is avail-

able, tested to military electrical specifications

DESCRIPTION:

The IDT72255/72265 are monolithic, CMOS, high capac-

ity, high speed, low power First-In, First-Out (FIFO) memories

with clocked read and write controls. These FIFOs are appli-

cable for a wide variety of data buffering needs, such as optical

disk controllers, local area networks (LANs), and inter-proces-

sor communication.

Both FIFOs have an 18-bit input port (D

) and an 18-bit

output port (Q

). The input port is controlled by a free-running

clock (WCLK) and a data input enable pin (

WEN

). Data is

written into the synchronous FIFO on every clock when

WEN

is asserted. The output port is controlled by another clock pin

(RCLK) and enable pin (

REN

). The read clock can be tied to

the write clock for single clock operation or the two clocks can

run asynchronously for dual clock operation. An output enable

pin (

) is provided on the read port for three-state control of

the outputs.

The IDT72255/72265 have two modes of operation: In the

IDT Standard Mode

, the first word written to the FIFO is

deposited into the memory array. A read operation is required

to access that word. In the

First Word Fall Through Mode

(FWFT), the first word written to an empty FIFO appears

FUNCTIONAL BLOCK DIAGRAM

WEN

WCLK

-D

LD SEN

•

INPUT REGISTER

OFFSET REGISTER

WRITE CONTROL

LOGIC

•

RAM ARRAY

8,192 x 18

16,384 x 18

FLAG

LOGIC

PAF

PAE

FWFT/SI

WRITE POINTER

READ POINTER

•

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

•

RCLK

REN

TIMING

-Q

3037 drw 01

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Integrated Device Technology, Inc

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

MAY 1997

DSC-3037/7

Recommended Resources

RC filter circuit b

One of the unijunction transistor trigger circuits

Safety bedside light switch

Circuit diagram 2 for changing the output voltage of secondary double-winding transformer

Negative voltage to positive voltage conversion circuit diagram 1

Sawtooth wave oscillator using 555 time base circuit

Development of virtual CD-ROM drive under Vista: Please give some examples or hints....; zhulinfeng6789 Embedded System

Design of an Error Amplifier for Active Voltage Down Control: Design of an Error Amplifier for Active Voltage Down Control...; linda_xia Analog electronics

Design of Video Monitoring Terminal Software: The monitoring terminal software of the video server is divided into three parts according to its functions: video acquisition, compression, and transmission. The development of this software is based...; wuyugwz Industrial Control Electronics

Lala this lost little lamb! ! Thank you! @!: [b][b]Hello seniors, I am a lost lamb. I am now a sophomore (majoring in network engineering). I want to choose embedded system as my career direction, but I don’t know what to do now? Is there any se...; 崔明义 Embedded System

Selection of low power LCD screen: I am an undergraduate student. I am currently using the MSP430 microcontroller to participate in a low-power application competition. The system's power consumption is required to be at the mW level, ...; RONDO7174 Microcontroller MCU

U disk IAP jump APP abnormal: [i=s]This post was last edited by shipeng on 2019-5-15 18:48[/i] [size=3]I recently used the USB_OTG_FS of STM32F429 to make a BOOTLOADER that can read files in the USB disk through USB (PA11, PA12) o...; shipeng stm32/stm8

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components