UT1553 Remote Terminal Multi-Protocol
F
EATURES
p
Complete MIL-STD-1553 Remote Terminal Interface
p
Mode selectable to comply with either MIL-STD-
p
p
p
p
p
p
p
p
p
p
p
p
p
1553A or MIL-STD-1553B bus protocol
Mil-STD-1773 compatible
Remote terminal operation is certified by ASD/
ENASC (SEAFAC)
Implements all dual-redundant Remote Terminal mode
codes and operational functions including broadcast
commands
Provides handshake control for quad-redundant
systems
Data pointers permit programmable memory mapping
for 1553 data over the entire 64K host memory space
Provides all handshaking signals for a DMA interface
Stores 1553 command word and time-tag information
with all incoming data for enhanced data management
Three-state address bus, databus, and control signals
simplify DMA operations
Supports end-of-command activity and data bus error
interrupts
Self-test capability
Available as a gate array macrocell
Available in 84-pin pingrid array, 84-lead leadless chip
carrier, or 84-lead flatpack packages
Standard Microcircuit Drawing 5962-88645 available
- QML Q compliant
I
NTRODUCTION
The UT1553 RTMP (figures 1 and 4) is a monolithic,
CMOS, VLSI integrated circuit that meets all requirements
for a dual-redundant MIL-STD-1553 Remote Terminal
interface. The RTMP’s advanced design supports both
MIL-STD-1553A and MIL-STD-1553B serial data bus
protocols, including differences in the status word response
time and bit definitions, providing the system designer a
single-chip solution to most Remote Terminal interface
requirements.
The UT1553 RTMP provides all requisite 1553 protocol and
data handling, 1553 message error checking, DMA
handshake and control signals, and comprehensive self-test
capabilities. The RTMP’s pointer-based, programmable
memory-mapping architecture permits the host to map 1553
message data anywhere in the 64K memory space. This
advanced memory mapping, along with the RTMP’s control
and status functions, minimize the host system’s 1553
interface overhead.
The UT1553 RTMP is a member of UTMC’s complete
family of high-reliability monolithic MIL-STD-1553
interface products.
MODE CODE/
SUBADDRESS
5
OUT
OUTPUT MULTIPLEXING AND
SELF- TES T WRAPAROUNDLOG IC
CHANNEL
A
IN
DECODER
TERMINAL
ADDRESS
5
MEMORY
ADDRESS
CONTROL
TIME TAG
CONTROL
BASE PTR
STATUS
LAST CMD
16
16
3
MEMORY
ADDRESS
COMMAND
RECOGNITION
DECODER
MUX
16
13
CONTROL
AND ERROR
LOGIC
CONTROL
INPUTS
CONTROL
OUTPUTS
OUT
CHANNEL
B
IN
9
CLOCK AND
RESET
LOGIC
ENCODER
DATA
TRANSFER
LOGIC
16
DATA
TIMER
LOGIC
MASTER 12MHz
RESET
Figure 1. UT1553 RTMP Functional Block Diagram
RTMP-1
Table of Contents
1.0
2.0
3.0
FUNCTIONAL DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
PIN IDENTIFICATION AND DESCRIPTION.
. . . . . . . . . . . . . . . . . . . . . . . . . . .5
REMOTE TERMINAL ARCHITECTURE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1 Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Read/Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3 Time Tag Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.5 Base Pointer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.6 Read Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.6.1 Operational Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.6.2 Last 1553 Command Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.7 Write Only Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
REMOTE TERMINAL INTERFACE OPERATION.
. . . . . . . . . . . . . . . . . . . . .17
4.1 Programming the BPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.2 RTMP Pointer Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3 Pointer Block Location Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.4 RTMP Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.5 RTMP Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.6 RTMP Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.6.1 Terminal Address Parity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.6.2 Framing or Overrun Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.6.3 1553 Message Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.7 RTMP Self-Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1553A AND 1553B MODES OF OPERATION
. . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.1 Status Word Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.2 Mode Code Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.3 Status Word Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
RTMP SYSTEM INTERFACE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6.1Assigning the Terminal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6.2Controlling the DMA Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6.3Interfacing with the RTMP’s Internal Register . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.4RTMP Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.4.1 RTMP -- 1553 Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.4.2 RTMP DMA Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MAXIMUM AND RECOMMENDED OPERATING CONDITIONS31
DC ELECTRICAL CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
AC ELECTRICAL CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
PACKAGE OUTLINE DRAWINGS.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.0
5.0
6.0
7.0
8.0
9.0
10.0
RTMP-2
F
UNCTIONAL
D
ESCRIPTION
General Description
The RTMP is an interface device linking a MIL-STD-1553
serial data bus and a host microprocessor system (figure 2).
By selecting the correct state of the 1553 protocol select pin
(PRA/B = 1 for 1553A, 0 for 1553B), the system designer
can program the RTMP to comply fully with either MIL-
STD-1553A or MIL-STD-1553B.
The link between the 1553 data bus and the RTMP is the
shared memory area. All the data the RTMP transmits or
receives over the 1553 bus is stored in this shared memory
area. The RTMP accesses the shared memory with its DMA
signals (DMAR, DMAG, and DMAEN), the 16-bit
bidirectional data bus (D0-D15), and the 16-bit address bus
(A0-A15).
Since the RTMP’s architecture is based on a series of data
pointers, the 1553 transmit and receive data can be placed
anywhere in the 64K memory space, allowing the system
designer to optimize memory usage. The system designer
can program the RTMP to store the data received over the
1553 bus in one of two ways. The RTMP can store the
received data in a single data buffer or in separate buffers.
When the RTMP stores the received data in a single buffer,
all received data, regardless of subaddress, is stored in
contiguous locations in the shared memory. When the
RTMP stores the received data in separate buffers, the
RTMP stores the data associated with each of the 30
subaddresses in unique locations in memory.
The RTMP has six internal registers that provide the host
subsystem with RTMP control and status information.
Three of these registers are read/write: Time Tag Data
Register (TTD), the Control Register (CTL), and the Base
Pointer Data Register (BPD). Two are read only:
Operational Status Register (OPS), and the Last Command
Register (LCM). The Stop Self-Test Register (SST) is a
write-only register. To control the RTMP and the 1553
interface, the host begins by programming the Base Pointer
Data Register. By programming the BPD, the system
designer tells the RTMP where in the shared memory the
64-word Pointer Block will reside, whether the RTMP will
store the 1553 received data in single or separate buffers,
and how deep these data buffers will actually be. Figure 3
is a simple representation of the RTMP’s memory-mapping
architecture.
After the host has programmed the BPD, the 1553 interface
is enabled by setting either CHAEN or CHBEN in the
RTMP’s Control Register. The RTMP now monitors the
1553 data bus for a valid command word or mode code to
its particular terminal address. When received, the RTMP
looks at the mode bit (single/separate) in the BPD, the 1553
command transmit/receive bit, and the mode code or
subaddress portion of the 1553 command to determine
which of the address pointers in the 64-word Pointer Block
the RTMP will use for this particular memory transaction.
Each memory transaction consists of memory writes for
receive command words and memory reads for transmit
command words. This process continues until all 1553 data
words have been received or transmitted. If the host has
enabled any of the RTMP’s interrupts, the RTMP asserts
them when the memory transaction is complete.
RTMP-3
64K x 16
SHARED RAM
ADDRESS BUS
HOST
UT1553 RTMP
DATA BUS
SUBSYSTEM
CONTROL
UT63M125
1553 TRANSCEIVER
1553 BUS A
1553 BUS B
Figure 2. RTMP General System Diagram
64K x 16
SHARED RAM
THESE TEN BITS FORM THE ADDRESS
OF THE STARTING LOCATION OF THE
64-WORD POINTER BLOCK.
0000H
MSB
B
P
A
6
BASE POINTER
DATA REGISTER
B
U
F
S
L
LSB
B BB B
S SS S
I I I I
Z ZZ Z
3 21 0
64-WORD
POINTER BLOCK
RECEIVE DATA
POINTER (30)
TRANSMIT DATA
POINTER (30)
BUFFER MODE SELECT
THE RECEIVE DATA BUFFER SIZE
IS PROGRAMMED WITH THESE FOUR BITS.
RECEIVE SUBADDRESS
DATA BUFFER -
8 TO 32K WORDS
TRANSMIT SUBADDRESS
DATA BUFFER
FFFFH
Figure 3. RTMP Receiveand Transmit Data Memory Mapping
RTMP-4
2.0 P
IN
I
DENTIFICATION
A
ND
D
ESCRIPTION
TAZ
TAO
TBZ
TBO
RAZ
RAO
RBZ
RBO
RTA0
RTA1
RTA2
RTA3
RTA4
RTPTY
MCSA0
MCSA1
MCSA2
MCSA3
MCSA4
EORT
EOMC
MERR
TIMERON
CHA/B
COMSTR
MC / S A
DMAR
*DMAG
*DMAEN
RD
WR
*CS
AV
RRD
RWR
**TAPEN
*SVC
**ILLCOM
**SME
**ENBC
PRA/B
**TEST
27
26
31
30
25
23
34
33
77
76
75
74
73
71
15
16
17
18
19
36
37
39
29
28
38
21
47
48
49
45
46
44
52
50
51
72
40
22
41
13
12
14
(L8)
(J7)
(K9)
(L10)
(K7)
(L6)
(J10)
(K10)
(B1)
(C2)
(B2)
(A1)
(B3)
(A3)
(L3)
(K4)
(L4)
(K6)
(K5)
(J11)
(H10)
(G9)
(L9)
(K8)
(H11)
(J5)
(F11)
(D11)
(D10)
(E11)
(E10)
(E9)
(C10)
(C11)
(B11)
(A2)
(G10)
(J6)
(G11)
(K3)
(K2)
(L2)
(B4)
(A4)
(A6)
(B5)
(C5)
(C6)
(B6)
(B7)
(C7)
(A8)
(B8)
(A9)
(A10)
(B9)
(B10)
(A11)
(L1)
(J2)
(K1)
(J1)
(H2)
(H1)
(G3)
(G2)
(G1)
(F1)
(E1)
(E2)
(F2)
(D1)
(D2)
(C1)
(L7)
(F9)
(A5)
(E3)
(F3)
(L5)
(F10)
(A7)
(K11)
(L11)
70
69
68
67
65
64
63
61
60
59
58
57
56
55
54
53
11
10
9
8
7
6
5
4
3
2
83
82
81
80
79
78
24
43
66
84
1
20
42
62
35
32
A 0 ++
A 1 ++
A 2 ++
A3
A4
A5
A6
ADDRESS
A7
A8
LINES
A9
A 10
A 11
A 12
A 13
A 14
A 15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D 10
D 11
D 12
D 13
D 14
D 15
BIPHASE
OUT
BIPHASE
IN
TERMINAL
ADDRESS
MODE CODE/
SUBADDRESS
STATUS
SIGNALS
DATA
LINES
DMA
SIGNALS
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
CLK
RESET
POWER
CONTROL
SIGNALS
GROUND
CLOCK
RESET
++
*
**
Bidirectional pin.
Pin internally pulled up.
Pin internally pulled down.
Leadless chip carrier pinnumbers are not in parentheses.
( ) Pingrid array pin numbers are in parentheses.
Figure 4. RTMP Functional Pin Description
RTMP-5
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