Flexible bus interface allows simple, low-cost designs
20, 25, 33, and 40MHz operation
Complete software support
— Optimizing compilers
— Real-time operating systems
— Monitors/debuggers
— Floating Point Software
— Page Description Languages
Clk2xIn
Clock
Generator
Unit
Master Pipeline Control
System Control
Coprocessor
Exception/Control
Registers
Memory Management
Registers
BrCond(3:0)
Integer
CPU Core
General Registers
(32 x 32)
ALU
Shifter
Int(5:0)
Translation
Lookaside Buffer
(64 entries)
Mult/Div Unit
Address Adder
PC Control
Virtual Address
32
Physical Address Bus
Instruction
Cache
(8kB/4kB)
Data Bus
Bus Interface Unit
4-deep
Write
Buffer
4-deep
Read
Buffer
DMA
Arbiter
Data
Cache
(2kB)
32
BIU
Control
Address/
Data
DMA
Ctrl
Rd/Wr
Ctrl
SysClk
2874 drw 01
Figure 1. R3051 Family Block Diagram
The IDT logo is a registered trademark, and RISChipset, RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400 and R4600 are trademarks of Integrated Device Technology, Inc.
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