Features
•
Six High-side and Six Low-side Drivers
•
Outputs Freely Configurable as Switch, Half Bridge or H-bridge
•
Capable to Switch All Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors
•
•
•
•
•
•
•
•
•
•
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and Inductors
0.6 A Continuous Current Per Switch
Low-side: R
DSon
< 1.5
Ω
Versus Total Temperature Range
High-side: R
DSon
< 2.0
Ω
Versus Total Temperature Range
Very Low Quiescent Current I
S
< 20 µA in Standby Mode
Outputs Short-circuit Protected
Overtemperature Prewarning and Protection
Under- and Overvoltage Protection
Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature
and Power Supply Fail
Serial Data Interface
Daisy Chaining Possible
SO28 Power Package
Dual Hex DMOS
Output Driver
with Serial Input
Control
U6815BM
Description
The U6815BM is a fully protected driver interface designed in 0.8-µm BCDMOS tech-
nology. It is used to control up to 12 different loads by a microcontroller in automotive
and industrial applications.
Each of the 6 high-side and 6 low-side drivers is capable to drive currents up to
600 mA. The drivers are freely configurable and can be controlled separately from a
standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors,
capacitors and inductors can be combined. The IC design especially supports the
applications of H-bridges to drive DC motors.
Protection is guaranteed in terms of short-circuit conditions, overtemperature, under-
and overvoltage. Various diagnostic functions and a very low quiescent current in
standby mode enable a wide range of applications. Automotive qualification referring
to conducted interferences, EMC protection and 2-kV ESD protection gives added
value and enhanced quality for the strict automotive requirements.
Rev. 4545B–BCD–12/02
1
Figure 1.
Block Diagram
HS1
15 15
HS2
13 13
HS3
12
HS4
3 3
HS5
2 2
HS6
28
28
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
5
V
S
V
S
10
26
DI
V
S
Osc
OV -
25
6
GND
CLK
S
I
24
S
C
T
O
L
D
H
S
6
L
S
6
H
S
5
L
S
5
H
S
4
L
S
4
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
protection
7
GND
V
S
CS
Input Register
Output Register
P
S
F
I
N
H
S
C
D
H
S
6
L
S
6
H
S
5
L
S
5
H
S
4
L
S
4
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
Control
logic
8
UV -
GND
protection
9
GND
INH
17
Thermal
protection
P - ON -
20
GND
18
DO
Reset
21
GND
Vcc
22
GND
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
23
GND
Vcc
19
Vcc
16
14
11
4
LS4
LS5
1
27
LS1
LS2
LS3
LS6
Pin Configuration
Figure 2.
Pinning SO28
HS6
28
LS6
27
DI
26
CLK
25
CS
24
GND GND GND GND VCC
23
22
21
20
19
DO
18
INH
17
LS1
16
HS1
15
U6815BM
Lead frame
1
LS5
2
HS5
3
4
5
VS
6
7
8
9
10
VS
11
LS3
12
HS3
13
HS2
14
LS2
HS4 LS4
GND GND GND GND
2
U6815BM
4545B–BCD–12/02
U6815BM
Pin Description
Pin
1
2
3
4
5
6, 7, 8, 9
10
11
12
13
14
15
16
17
18
Symbol
LS5
HS5
HS4
LS4
VS
GND
VS
LS3
HS3
HS2
LS2
HS1
LS1
INH
DO
Function
Low-side driver output 5, power-MOS open drain with internal reverse diode, overvoltage protection by
active zenering, short-circuit protection, diagnosis for short and open load
High-side driver output 5, power-MOS open drain with internal reverse diode, overvoltage protection by
active zenering, short-circuit protection, diagnosis for short and open load
High-side driver output 4 (see Pin 2)
Low-side driver output 4 (see Pin 1)
Power supply output stages HS4, HS5, HS6, internal supply; external connection to Pin 10 necessary
Ground, reference potential, internal connection to Pin 20 - 23, cooling tab
Power supply output stages HS1, HS2 and HS3
Low-side driver output 3 (see Pin 1)
High-side driver output 3 (see Pin 2)
High-side driver output 2 (see Pin 2)
Low-side driver output 2 (see Pin 1)
High-side driver output 1 (see Pin 2)
Low-side driver output 1 (see Pin 1)
Inhibit input, 5-V logic input with internal pull down, low = standby, high = normal operating
Serial data output, 5-V CMOS logic level tristate output for output (status) register data, sends 16-bit
status information to the microcontroller (LSB is transferred first).
Output will remain tristated unless device is selected by CS = low, therefore, several ICs can operate
on one data output line only.
Logic supply voltage (5 V)
Ground (see Pins 6 - 9)
Chip select input, 5-V CMOS logic level input with internal pull up, low = serial communication is
enabled, high = disabled
Serial clock input, 5-V CMOS logic level input with internal pull down, controls serial data input
interface and internal shift register (f
max
= 2 MHz)
Serial data input, 5-V CMOS logic level input with internal pull down, receives serial data from the
control device, DI expects a 16-bit control word with LSB being transferred first
Low-side driver output 6 (see Pin 1)
High-side driver output 6 (see Pin 2)
19
20, 21, 22, 23
24
25
26
27
28
VCC
GND
CS
CLK
DI
LS6
HS6
3
4545B–BCD–12/02
Functional Description
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI syn-
chronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0,
SRR) has to be transferred first. Execution of new input data is enabled on the rising
edge of the CS signal. When CS is high, Pin DO is in tristate condition. This output is
enabled on the falling edge of CS. Output data will change their state with the rising
edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is
transferred first.
Figure 3.
Data Transfer
CS
DI
SRR
0
1
LS1
HS1
2
3
LS2
HS2
4
5
LS3
HS3
6
7
LS4
HS4
8
9
LS5
HS5
10
LS6
11
HS6
12
OLD
13
SCT
14
SI
15
CLK
DO
TP
SLS1
SHS1
SLS2
SHS2
SLS3
SHS3
SLS4
SHS4
SLS5
SHS5
SLS6
SHS6
SCD
INH
PSF
Input Data Protocol
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Input Register
SRR
LS1
HS1
LS2
HS2
LS3
HS3
LS4
HS4
LS5
HS5
LS6
HS6
OLD
SCT
SI
Function
Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the output
data register are set to low)
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
See LS1
See HS1
See LS1
See HS1
See LS1
See HS1
See LS1
See HS1
See LS1
See HS1
Open load detection (low = on)
Programmable time delay for short circuit and overvoltage shutdown (short circuit shutdown delay
high/low = 100 ms/12.5 ms, overvoltage shutdown delay high/low = 15 ms/3.5 ms
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part is still powered)
4
U6815BM
4545B–BCD–12/02
U6815BM
After power-on reset, the input register has the following status:
Bit 15
(SI)
H
Bit 14
(SCT)
H
Bit 13
(OLD)
H
Bit 12
(HS6)
L
Bit 11
(LS6)
L
Bit 10
(HS5)
L
Bit 9
(LS5)
L
Bit 8
(HS4)
L
Bit 7
(LS4)
L
Bit 6
(HS3)
L
Bit 5
(LS3)
L
Bit 4
(HS2)
L
Bit 3
(LS2)
L
Bit 2
(HS1)
L
Bit 1
(LS1)
L
Bit 0
(SRR)
L
Output Data Protocol
Bit
0
1
Output (Status) Register
TP
Status LS1
Function
Temperature prewarning: high = warning (overtemperature shut down)
(1)
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load (correct load condition is detected
if the corresponding output is switched off)
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load (correct load condition is detected
if the corresponding output is switched off)
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Short circuit detected: set high, when at least one output is switched off by a short circuit
condition
Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (Pin 17).
High = standby, low = normal operation
Power supply fail: over- or undervoltage at Pin VS detected
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Note:
Status HS1
Status LS2
Status HS2
Status LS3
Status HS3
Status LS4
Status HS4
Status LS5
Status HS5
Status LS6
Status HS6
SCD
INH
PSF
1. Bit 0 to 15 = high: overtemperature shutdown
Power Supply Fail
In case of over-/undervoltage at Pin VS, an internal timer is started. When the overvolt-
age delay time (t
dOV
) programmed by the SCT Bit, or the undervoltage delay time (t
dUV
)
is reached, the power supply fail bit (PSF) in the output register is set and all outputs are
disabled. When normal voltage is present again, the outputs are enabled immediately.
The PSF bit remains high until it is reset by the SRR bit in the input register.
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side
switch and a pull-down current for each low-side switch is turned on (open-load detec-
tion current I
HS1-6
, I
LS1-6
). If V
VS
-V
HS1-6
or V
LS1-6
is lower than the open-load detection
threshold (open-load condition) the corresponding bit of the output in the output register
is set to high. Switching on an output stage with OLD bit set to low disables the open-
load function for this output.
Open-load Detection
5
4545B–BCD–12/02
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