DATASHEET
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI,
and FBDIMM
Description
DB1200 Rev 2.0 Intel Yellow Cover Device
9DB1200C
Features/Benefits
•
•
•
3 selectable SMBus addresses for easy system expansion
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
Supports undriven differential outputs in Power Down Mode
for power management.
General Description
The ICS9DB1200 is an Intel DB1200 Differential Buffer
Specification device. This buffer provides 12 differential clocks
at frequencies ranging from 100MHz to 400 MHz. The
ICS9DB1200 is driven by a differential output from a CK410B+
or CK509B main clock generator.
Key Specifications
•
•
•
•
•
•
Output cycle-cycle jitter < 50ps.
Output to output skew: 50ps
Phase jitter: PCIe Gen2 < 3.1ps rms
Phase jitter: QPI < 0.5ps rms
64-pin TSSOP Package
Available in RoHS compliant packaging
Output Features
•
•
•
•
•
12 - 0.7V current-mode differential output pairs.
Supports zero delay buffer mode and fanout mode.
Bandwidth programming available.
100-400 MHz operation in PLL mode
33-400 MHz operation in Bypass mode
Functional Block Diagram
12
OE_(11:0)#
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
12
DIF(11:0))
FS(2:0)
HIGH_BW#
BYPASS#/PLL
VTTPWRGD#/PD
ADR_SEL
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT
®
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
1414G—08/15/12
1
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
Pin Configuration
VDD
DIF_IN
DIF_IN#
GND
OE0#
DIF_0
DIF_0#
VDD
GND
OE1#
DIF_1
DIF_1#
OE2#
DIF_2
DIF_2#
GND
VDD
OE3#
DIF_3
DIF_3#
OE4#
DIF_4
DIF_4#
VDD
GND
OE5#
DIF_5
DIF_5#
**ADR_SEL
HIGH_BW#
FS2
SMBCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDA
AGND
IREF
FS0
OE11#
DIF_11
DIF_11#
VDD
GND
OE10#
DIF_10
DIF_10#
OE9#
DIF_9
DIF_9#
GND
VDD
OE8#
DIF_8
DIF_8#
OE7#
DIF_7
DIF_7#
VDD
GND
OE6#
DIF_6
DIF_6#
VTTPWRGD#/PD
BYPASS#/PLL
FS1
SMBDAT
64-TSSOP
** Indicates 120K ohm Pulldown
9DB1200C
Frequency Select Table
FS
L
2
FS
L
1
FS
L
0
B0b2
B0b1
B0b0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Input
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
Hi-Z
DIF_x;
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
Hi-Z
SMBus Address Selection (Pin 29)
ADR_SEL
Voltage
SMBus Adr (Wr/Rd)
Low
<0.8V
DC/DD
Mid
1.2<Vin<1.8V
D6/D7
High
Vin > 2.0V
D4/D5
Power Groups
Pin Number
VDD
GND
1
4
8, 17, 24, 41, 9, 16, 25, 40,
48, 57
49, 56
N/A
63
Description
DIF_IN/DIF_IN#
DIF(11:0)
1. FS
L
(2:0) are 3.3V tolerant low-threshold inputs.
Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
IREF
Analog VDD & GND
64
63
for PLL core
Note: Please treat pin 1 as an analog VDD.
1414G—08/15/12
IDT
®
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
2
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD
DIF_IN
DIF_IN#
GND
OE0#
DIF_0
DIF_0#
VDD
GND
OE1#
DIF_1
DIF_1#
OE2#
DIF_2
DIF_2#
GND
VDD
OE3#
DIF_3
DIF_3#
OE4#
DIF_4
DIF_4#
VDD
GND
OE5#
DIF_5
DIF_5#
**ADR_SEL
HIGH_BW#
FS2
SMBCLK
PIN NAME
TYPE
PWR
IN
IN
PWR
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
IN
IN
IN
DESCRIPTION
Power supply, nominal 3.3V
0.7 V Differential TRUE input
0.7 V Differential Complementary Input
Ground pin.
Active low input for enabling DIF pair 0.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 1.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 2.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Active low input for enabling DIF pair 3.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 4
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
This tri-level input selects one of 3 SMBus addresses. See the SMBus
Address Select Table for the addresses.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Frequency select pin.
Clock pin of SMBUS circuitry, 5V tolerant
IDT
®
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
1414G—08/15/12
3
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
Pin Description
PIN #
33
34
35
SMBDAT
FS1
BYPASS#/PLL
PIN NAME
TYPE
I/O
IN
IN
DESCRIPTION
Data pin of SMBUS circuitry, 5V tolerant
3.3V Frequency select latched input pin.
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
VTTPWRGD# is an active low input used to sample latched inputs and
allow the device to Power Up. PD is an asynchronous active high input
pin used to put the device into a low power state. The internal clocks and
PLLs are stopped.
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 10.
1 = tri-state outputs, 0 = enable outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 11.
1 = tri-state outputs, 0 = enable outputs
3.3V Frequency select latched input pin.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Analog Ground pin for Core PLL
3.3V power for the PLL core.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VTTPWRGD#/PD
DIF_6#
DIF_6
OE6#
GND
VDD
DIF_7#
DIF_7
OE7#
DIF_8#
DIF_8
OE8#
VDD
GND
DIF_9#
DIF_9
OE9#
DIF_10#
DIF_10
OE10#
GND
VDD
DIF_11#
DIF_11
OE11#
FS0
IREF
AGND
VDDA
IN
OUT
OUT
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
PWR
PWR
OUT
OUT
IN
IN
OUT
PWR
PWR
IDT
®
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
1414G—08/15/12
4
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
Absolute Max
Symbol
VDDA
VDD
V
IL
V
IH
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
Max
4.6
4.6
V
DD
+0.5V
-65
0
150
70
115
Units
V
V
V
V
C
°C
°C
V
°
GND-0.5
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
V
IH
V
IL
I
IH
I
IL1
Input Low Current
I
IL2
Operating Supply Current
Powerdown Current
Input Frequency
Pin Inductance
Capacitance
PLL Jitter Peaking
PLL Bandwidth
Clk Stabilization
Modulation Frequency
OE# Latency
Tdrive_PD
Tfall
Trise
1
CONDITIONS
3.3 V +/-5%
3.3 V +/-5%
V
IN
= V
DD
V
IN
= 0 V; Inputs with no pull-up
resistors
V
IN
= 0 V; Inputs with pull-up resistors
Full Active, C
L
= Full load;
all differential pairs tri-stated
PLL Mode
Bypass Mode
Logic Inputs
Output pin capacitance
Peaking when HIGH_BW#=0
Peaking when HIGH_BW#=1
PLL Bandwidth when HIGH_BW#=0
PLL Bandwidth when HIGH_BW#=1
From V
DD
Power-Up and after input
clock stabilization or de-assertion of
PD# to 1st clock
Triangular Modulation
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD de-assertion
Fall time of OE#
Rise time of OE#
MIN
2
GND - 0.3
-5
-5
-200
TYP
MAX
V
DD
+ 0.3
0.8
5
UNITS NOTES
V
V
uA
uA
uA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1,2
1
1,3
1,3
1
1
I
DD3.3OP
I
DD3.3PD
F
iPLL
F
iBYPASS
L
pin
C
IN
C
OUT
j
PEAK
BW
T
STAB
f
MOD
t
LATOE#
t
DRVPD
t
F
t
R
375
24
400
400
7
5
6
2
2
4
1.4
1.8
30
4
33
12
300
5
5
mA
mA
MHz
MHz
nH
pF
pF
dB
dB
MHz
MHz
ms
kHz
cycles
us
ns
ns
100
33
1.5
1.5
1.5
3
1
2
0.7
Guaranteed by design and characterization, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Time from deassertion until outputs are >200 mV
IDT
®
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
1414G—08/15/12
5
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