GS81313LT18GK-714T datasheet, PDF

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GS81313LT18GK-714T: DescriptionDDR SRAM, 8MX18, CMOS, PBGA260, 14 X 22 MM, 1 MM PITCH, ROHS COMPLIANT, BGA-260; Categorystorage storage; File Size378KB，29 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS81313LT18GK-714T Overview

DDR SRAM, 8MX18, CMOS, PBGA260, 14 X 22 MM, 1 MM PITCH, ROHS COMPLIANT, BGA-260

GS81313LT18GK-714T Parametric

Parameter Name	Attribute value
Maker	GSI Technology
package instruction	HBGA,
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
JESD-30 code	R-PBGA-B260
length	22 mm
memory density	150994944 bit
Memory IC Type	DDR SRAM
memory width	18
Number of functions	1
Number of terminals	260
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	8MX18
Package body material	PLASTIC/EPOXY
encapsulated code	HBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, HEAT SINK/SLUG
Parallel/Serial	PARALLEL
Maximum seat height	2.3 mm
Maximum supply voltage (Vsup)	1.35 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	1.25 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	14 mm
Base Number Matches	1

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Preliminary

GS81313LT18/36GK-833/714/625

260-Pin BGA

Commercial Temp

Industrial Temp

Features

•

4Mb x 36 and 8Mb x 18 organizations available

833 MHz maximum operating frequency

833 MT/s peak transaction rate (in millions per second)

60 Gb/s peak data bandwidth (in x36 devices)

Common I/O DDR Data Bus

Non-multiplexed SDR Address Bus

One operation - Read or Write - per clock cycle

Burst of 2 Read and Write operations

3 cycle Read Latency

On-chip ECC with virtually zero SER

1.2V ~ 1.3V core voltage

1.2V ~ 1.3V HSTL I/O interface

Configurable ODT (on-die termination)

ZQ pin for programmable driver impedance

ZT pin for programmable ODT impedance

IEEE 1149.1 JTAG-compliant Boundary Scan

260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-

compliant BGA package

144Mb SigmaDDR-IIIe™

Burst of 2 ECCRAM™

Clocking and Addressing Schemes

Up to 833 MHz

1.2V ~ 1.3V V

DDQ

The GS81313LT18/36GK SigmaDDR-IIIe ECCRAMs are

synchronous devices. They employ three pairs of positive and

negative input clocks; one pair of master clocks, CK and CK,

and two pairs of write data clocks, KD[1:0] and KD[1:0]. All

six input clocks are single-ended; that is, each is received by a

dedicated input buffer.

CK and CK are used to latch address and control inputs, and to

control all output timing. KD[1:0] and KD[1:0] are used solely

to latch data inputs.

Each internal read and write operation in a SigmaDDR-IIIe B2

ECCRAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaDDR-IIIe B2 ECCRAM is always one address

pin less than the advertised index depth (e.g. the 8M x 18 has

4M addressable index).

SigmaDDR-IIIe™ Family Overview

SigmaDDR-IIIe ECCRAMs are the Common I/O half of the

SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance

ECCRAMs. Although very similar to GSI's second generation

of networking SRAMs (the SigmaQuad-II/SigmaDDR-II

family), these third generation devices offer several new

features that help enable significantly higher performance.

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by SER events such as cosmic rays, alpha particles,

etc. The resulting Soft Error Rate of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no on-chip ECC,

which typically have an SER of 200 FITs/Mb or more.

All quoted SER values are at sea level in New York City.

Parameter Synopsis

Speed Grade

-833

-714

-625

Max Operating Frequency

833 MHz

714 MHz

625 MHz

Read Latency

3 cycles

1.2V to 1.35V

1.15V to 1.35V

Rev: 1.09a 10/2015

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS81313LT18GK-714T Related Products

	GS81313LT18GK-714T	GS81313LT18GK-625T	GS81313LT18GK-833IT
Description	DDR SRAM, 8MX18, CMOS, PBGA260, 14 X 22 MM, 1 MM PITCH, ROHS COMPLIANT, BGA-260	DDR SRAM, 8MX18, CMOS, PBGA260, 14 X 22 MM, 1 MM PITCH, ROHS COMPLIANT, BGA-260	DDR SRAM, 8MX18, CMOS, PBGA260, 14 X 22 MM, 1 MM PITCH, ROHS COMPLIANT, BGA-260
Maker	GSI Technology	GSI Technology	GSI Technology
package instruction	HBGA,	HBGA,	HBGA,
Reach Compliance Code	compliant	compliant	compliant
ECCN code	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B
JESD-30 code	R-PBGA-B260	R-PBGA-B260	R-PBGA-B260
length	22 mm	22 mm	22 mm
memory density	150994944 bit	150994944 bit	150994944 bit
Memory IC Type	DDR SRAM	DDR SRAM	DDR SRAM
memory width	18	18	18
Number of functions	1	1	1
Number of terminals	260	260	260
word count	8388608 words	8388608 words	8388608 words
character code	8000000	8000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
organize	8MX18	8MX18	8MX18
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HBGA	HBGA	HBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, HEAT SINK/SLUG	GRID ARRAY, HEAT SINK/SLUG	GRID ARRAY, HEAT SINK/SLUG
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL
Maximum seat height	2.3 mm	2.3 mm	2.3 mm
Maximum supply voltage (Vsup)	1.35 V	1.35 V	1.35 V
Minimum supply voltage (Vsup)	1.2 V	1.15 V	1.2 V
Nominal supply voltage (Vsup)	1.25 V	1.2 V	1.25 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Terminal form	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
width	14 mm	14 mm	14 mm
Base Number Matches	1	1	1
Maximum operating temperature	85 °C	85 °C	-
Temperature level	OTHER	OTHER	-

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