HD74AC273
Octal D-Type Flip-Flop
ADE-205-386 (Z)
1st. Edition
Sep. 2000
Description
The HD74AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The
common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High
clock transition, is transferred to the corresponding flip-flops’s Q output
All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the
MR
input. The device is useful for applications where the true output only is required and the Clock and Master
Reset are common to all storage elements.
Features
•
Ideal Buffer for MOS Microprocessor or Memory
•
Eight Edge-Triggered D Flip-Flops
•
Buffered Common Clock
•
Buffered, Asynchronous Master Reset
•
See HD74AC373 for Transparent Latch Version
•
See HD74AC374 for 3-State Version
•
Outputs Source/Sink 24 mA
HD74AC273
Logic Diagram
D
0
CP
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
CP
R
D
MR
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Mode Select-Truth Table
Inputs
Operating Mode
Reset (Clear)
Load “1”
Load “0”
H :
L :
X :
:
MR
L
H
H
CP
X
D
n
X
H
L
Outputs
Q
n
L
H
L
High Voltage Level
Low Voltage Level
Immaterial
Low-to-High Clock Transition
DC Characteristics
(unless otherwise specified)
Item
Maximum quiescent supply current
Maximum quiescent supply current
Symbol
I
CC
I
CC
Max
80
8.0
Unit
µA
µA
Condition
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25°C
3
HD74AC273
AC Characteristics: HD74AC273
Ta = +25°C
C
L
= 50 pF
Item
Maximum clock
frequency
Propagation delay
Clock to output
Propagation delay
Clock to output
Propagation delay
MR
to output
Note:
t
PHL
t
PHL
t
PLH
Symbol
f
max
V
CC
(V)*
1
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Min
90
140
1.0
1.0
1.0
1.0
1.0
1.0
Typ
125
175
7.0
5.5
7.0
5.0
7.0
5.0
Max
—
—
12.5
9.0
13.0
10.0
13.0
10.0
Ta = –40°C to +85°C
C
L
= 50 pF
Min
75
125
1.0
1.0
1.0
1.0
1.0
1.0
Max
—
—
14.0
10.0
14.5
11.0
14.0
10.5
ns
ns
ns
Unit
MHz
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
AC Operating Requirements: HD74AC273
Ta = +25°C
C
L
= 50 pF
Item
Setup time, HIGH or LOW
Data to CP
Hold time, HIGH or LOW
Data to CP
Clock pulse width
HIGH or LOW
MR
Pulse width
HIGH or LOW
Recovery time
MR
to CP
Note:
t
rec
t
w
t
w
t
h
Symbol
t
su
V
CC
(V)*
1
Typ
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.5
2.5
–2.0
–1.0
3.5
2.5
2.0
1.5
1.5
1.0
Ta = –40°C
to +85°C
C
L
= 50 pF
Guaranteed Minimum
5.5
4.0
0.0
1.0
5.5
4.0
5.5
4.0
3.5
2.0
6.0
4.5
0.0
1.0
6.0
4.5
6.0
4.5
4.5
3.0
ns
ns
ns
ns
Unit
ns
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
4
京公网安备 11010802033920号
EEWORLD
