IS61LV25616
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
• High-speed access time:
— 7, 8, 10, 12, and 15 ns
• CMOS low power operation
• Low stand-by power:
— Less than 5 m
A
(typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
ISSI
®
AUGUST 2000
DESCRIPTION
The
ISSI
IS61LV25616 is a high-speed, 4,194,304-bit static
RAM organized as 262,144 words by 16 bits. It is fabricated
using
ISSI
's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design tech-
niques, yields high-performance and low power consumption
devices.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE.
The active LOW Write
Enable (WE) controls both writing and reading of the memory.A
data byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IS61LV25616 is packaged in the JEDEC standard
44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and
48-pin Mini BGA (8mm x 10mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
CONTROL
CIRCUIT
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
1
IS61LV25616
PIN CONFIGURATIONS
44-Pin TSOP (Type II) and SOJ
44-Pin LQFP
ISSI
®
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
44 43 42 41 40 39 38 37 36 35 34
33
1
32
2
31
3
30
4
29
5
TOP VIEW
28
6
27
7
26
8
25
9
24
10
23
11
12 13 14 15 16 17 18 19 20 21 22
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A17
A16
A15
A14
A13
A12
A11
A10
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
48-Pin mini BGA
1
2
3
4
5
6
PIN DESCRIPTIONS
A0-A17
I/O0-I/O15
CE
OE
WE
LB
UB
NC
Vcc
GND
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
A
B
C
D
E
F
G
H
LB
I/O
8
I/O
9
GND
Vcc
I/O
14
I/O
15
NC
OE
UB
I/O
10
I/O
11
I/O
12
I/O
13
NC
A8
A0
A3
A5
A17
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A11
N/C
I/O
0
I/O
2
Vcc
GND
I/O
6
I/O
7
NC
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
IS61LV25616
TRUTH TABLE
WE
X
H
X
H
H
H
L
L
L
CE
H
L
L
L
L
L
L
L
L
OE
X
H
X
L
L
L
X
X
X
LB
X
X
H
L
H
L
L
H
L
UB
X
X
H
H
L
L
H
L
L
I/O PIN
I/O0-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
D
IN
High-Z
D
IN
High-Z
High-Z
High-Z
High-Z
D
OUT
D
OUT
High-Z
D
IN
D
IN
ISSI
Vcc Current
I
SB
1
, I
SB
2
I
CC
I
CC
®
Mode
Not Selected
Output Disabled
Read
1
2
3
4
5
Write
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter
V
TERM
T
BIAS
V
CC
T
STG
P
T
Terminal Voltage with Respect to GND
Temperature Under Bias
Vcc Related to GND
Storage Temperature
Power Dissipation
Value
–0.5 to Vcc+0.5
–45 to +90
–0.3 to +4.0
–65 to +150
1.0
Unit
V
°C
V
°C
W
6
7
8
9
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
10
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
7, 8, 10 ns
V
CC
3.3V +10%, -5%
3.3V +10%, -5%
12 ns, 15 ns
V
CC
3.3V ± 10%
3.3V ± 10%
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
3
IS61LV25616
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
, 4
Outputs Disabled
Com.
Ind.
Com.
Ind.
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.0
–0.3
–1
–5
–1
–5
ISSI
Max.
—
0.4
V
CC
+ 0.3
0.8
1
5
1
5
Unit
V
V
V
V
µA
µA
®
Notes:
1. V
IL
(min.) = –2.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
I
CC
I
SB
Parameter
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
Com.
I
OUT
= 0 mA, f = f
MAX
Ind.
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = f
MAX
.
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
Com.
Ind.
Com.
Ind.
-7, -8
Min. Max.
—
—
—
—
—
—
—
—
260
300
85
95
20
25
10
15
-10
Min. Max.
—
—
—
—
—
—
—
—
260
300
85
95
20
25
10
15
-12
Min. Max.
—
—
—
—
—
—
—
—
240
280
75
85
20
25
10
15
-15
Min. Max.
—
—
—
—
—
—
—
—
220
250
65
75
20
25
10
15
Unit
mA
mA
I
SB
1
mA
I
SB
2
V
CC
= Max.,
Com.
CE
≥
V
CC
– 0.2V,
Ind.
V
IN
≥
V
CC
– 0.2V, or
V
IN
≤
0.2V, f = 0
mA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Shaded area product in development
CAPACITANCE
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
IS61LV25616
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
OE
to High-Z Output
OE
to Low-Z Output
CE
to High-Z Output
CE
to Low-Z Output
LB, UB
Access Time
LB, UB
to High-Z Output
LB, UB
to Low-Z Output
Power Up Time
Power Down Time
-7
Min. Max.
7
—
3
—
—
—
0
0
2.5
—
0
0
0
—
—
7
—
7
3.5
2.5
—
3
—
3
2.5
—
—
7
-8
Min. Max.
8
—
3
—
—
—
0
—
3
—
0
0
0
—
—
8
—
8
3.5
3
—
3
—
3.5
3
—
—
8
-10
Min. Max.
10
—
3
—
—
—
0
0
3
—
0
0
0
—
—
10
—
10
4
4
—
4
—
4
3
—
—
10
-12
Min. Max.
12
—
3
—
—
—
0
0
3
—
0
0
0
—
—
12
—
12
5
5
—
6
—
5
4
—
—
12
ISSI
-15
Min. Max.
15
—
3
—
—
0
0
0
3
—
0
0
0
—
—
15
—
15
7
6
—
8
—
7
5
—
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
1
2
3
4
5
6
7
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
HZOE
(2)
t
LZOE
(2)
t
HZCE
(2
t
LZCE
(2)
t
BA
t
HZB
(2)
t
LZB
(2)
t
PU
t
PD
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V,
input pulse levels of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
Shaded area product in development
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
8
9
319
Ω
AC TEST LOADS
10
50Ω
1.5V
30 pF
Including
jig and
scope
Z
O
= 50Ω
OUTPUT
3.3V
11
OUTPUT
5 pF
Including
jig and
scope
353
Ω
12
Figure 1
Figure 2
5
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
Analog electronics
京公网安备 11010802033920号
EEWORLD
