W3E64M72S-XSBX
64Mx72 DDR SDRAM
FEATURES
Data rate = 200, 250, 266 and 333Mbs**
Package:
• 219 Plastic Ball Grid Array (PBGA), 25 x 32mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR) architecture; two
data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/received with
data, i.e., source-synchronous data capture (one per byte)
DQS edge-aligned with data for READs; center-aligned with
data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) pins for masking write data
(one per byte)
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military TemperatureRanges
Organized as 64M x 72
Weight: W3E64M72S-XSBX - 4.5 grams typical
GENERAL DESCRIPTION
The 512MByte (4Gb) DDR SDRAM is a high-speed CMOS, dynamic
random-access, memory using 9 chips containing 536,870,912 bits.
Each chip is internally configured as a quad-bank DRAM.
The 512MB DDR SDRAM uses a double data rate architecture to
achieve high-speed operation. The double data rate architecture is
essentially a 2n-prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins. A single read
or write access for the 512MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the internal
DRAM core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted externally, along
with data, for use in data capture at the receiver.strobe transmitted
by the DDR SDRAM during READs and by the memory contoller
during WRITEs. DQS is edge-aligned with data for READs and
center-aligned with data for WRITEs. Each chip has two data
strobes, one for the lower byte and one for the upper byte.
The 512MB DDR SDRAM operates from a differential clock (CK
and CK#); the crossing of CK going HIGH and CK# going LOW
will be referred to as the positive edge of CK. Commands (address
and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered coincident
with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE
burst lengths of 2, 4, or 8 locations. An auto precharge function may
be enabled to provide a self-timed row precharge that is initiated
at the end of the burst access.
The pipelined, multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective bandwidth by
hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-saving
power-down mode. All inputs are compatible with the Jedec
Standard for SSTL_2. All full drive options outputs are SSTL_2,
Class II compatible.
BENEFITS
66% Space Savings vs. TSOP
Reduced part count
55% I/O reduction vs TSOP
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
* This product is subject to change without notice. This product has been qualified for commercial
and industrial temperature ranges.
** For 333Mbs operation of Industrial temperature CL = 2.5, at Military temperature CL = 3.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command which is then followed
by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank, A0-12 select
the row). The address bits registered coincident with the READ or
Microsemi Corporation reserves the right to change products or specifications without notice.
October 2010
Rev. 6
© 2010 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3E64M72S-XSBX
DENSITY COMPARISONS
ACTUAL SIZE
25
W3E64M72S-XSBX
32
Area = 800mm
2
I/O Count = 219 Balls
SAVINGS
– Area: 66% – I/O Count: 55%
Discrete Approach
11.9
11.9
11.9
11.9
11.9
11.9
11.9
11.9
11.9
22.3
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
Area: 9 x 265mm
2
= 2,385mm
2
I/O Count: 9 x 54 pins = 486 pins
WRITE command are used to select the starting column location
for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized.
The following sections provide detailed information covering device
initialization, register definition, command descriptions and device
operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified may
result in undefined operation. Power must
fi
rst be applied to V
CC
and V
CCQ
simultaneously, and then to V
REF
(and to the system
V
TT
). V
TT
must be applied after V
CCQ
to avoid device latch-up,
which may cause permanent damage to the device. V
REF
can
be applied any time after V
CCQ
but is expected to be nominally
coincident with V
TT
. Except for CKE, inputs are not recognized
as valid until after VREF is applied. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after V
CC
is applied. After CKE
passes through V
IH
, it will transition to an SSTL_2 signal and
remain as such until power is cycled. Maintaining an LVCMOS
LOW level on CKE during power-up is required to ensure that the
DQ and DQS outputs will be in the High-Z state, where they will
remain until driven in normal operation (by a read access). After all
power supply and reference voltages are stable, and the clock is
stable, the DDR SDRAM requires a 200μs delay prior to applying
an executable command.
Microsemi Corporation reserves the right to change products or specifications without notice.
October 2010
Rev. 6
© 2010 Microsemi Corporation. All rights reserved.
2
Once the 200μs delay has been satisfied, a DESELECT or NOP
command should be applied, and CKE should be brought HIGH.
Following the NOP command, a PRECHARGE ALL command
should be applied. Next a LOAD MODE REGISTER command
should be issued for the extended mode register (BA1 LOW and
BA0 HIGH) to enable the D
LL
, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1 both LOW)
to reset the D
LL
and to program the operating parameters. Two-
hundred clock cycles are required between the DLL reset and any
READ command. A PRECHARGE ALL command should then be
applied, placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
performed (t
RFC
must be satisfied.) Additionally, a LOAD MODE
REGISTER command for the mode register with the reset DLL
bit deactivated (i.e., to program operating parameters without
resetting the DLL) is required. Following these requirements, the
DDR SDRAM is ready for normal operation.
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3E64M72S-XSBX
FIGURE 1 – PIN CONFIGURATION
Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQ1
DQ3
DQ6
DQ7
CAS0#
CS0#
V
SS
V
SS
CLK3#
NC
DQ56
DQ57
DQ60
DQ62
V
SS
2
DQ0
DQ2
DQ4
DQ5
DQML0
WE0#
RAS0#
V
SS
V
SS
CKE3
CLK3
DQMH3
DQ58
DQ59
DQ61
DQ63
3
DQ14
DQ12
DQ10
DQ8
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
DQ55
DQ53
DQ51
DQ49
4
DQ15
DQ13
DQ11
DQ9
DQMH0
CLK0
CKE0
V
CCQ
V
CCQ
CS3#
CAS3#
WE3#
DQ54
DQ52
DQ50
DQ48
5
V
SS
V
SS
V
CC
V
CCQ
DQSH3
DQSL3
CLK0#
V
SS
V
SS
DQSL4
RAS3#
DQML3
NC
V
SS
V
CC
V
CCQ
6
V
SS
V
SS
V
CC
V
CCQ
DQSL0
7
A9
A0
A2
A12
DQSH0
8
A10
A7
A5
DNU
BA0
9 10
A11
A6
A4
DNU
BA1
A8
A1
A3
DNU
DQSL1
11 12 13 14 15 16
V
CCQ
V
CC
V
SS
V
SS
DQSH1
V
CCQ
V
CC
V
SS
V
SS
V
REF
RAS1#
CAS1#
V
CC
V
CC
CLK2#
DQSL2
DQ16
DQ18
DQ20
DQ22
DQML1
WE1#
CS1#
V
SS
V
SS
CKE2
CLK2
DQMH2
DQ41
DQ43
DQ45
DQ47
DQ17
DQ19
DQ21
DQ23
V
SS
V
SS
V
SS
Vss
V
SS
V
SS
V
SS
V
SS
DQ40
DQ42
DQ44
DQ46
DQ31
DQ29
DQ27
DQ26
NC
DQMH1
CLK1#
V
CCQ
V
CCQ
RAS2#
WE2#
DQML2
DQ37
DQ36
DQ34
DQ32
V
SS
DQ30
DQ28
DQ25
DQ24
CLK1
CKE1
V
CC
V
CC
CS2#
CAS2#
DQ39
DQ38
DQ35
DQ33
V
CC
CKE4
CLK4#
V
SS
V
CC
V
CCQ
NC
NC
NC
NC
NC
CLK4
NC
NC
NC
NC
CAS4#
DQ71
DQ69
DQ67
DQ65
WE4#
DQ70
DQ68
DQ66
DQ64
RAS4#
DQML4
V
CC
V
SS
V
SS
CS4#
DQSH2
V
CC
V
SS
V
SS
NOTE: DNU = Do Not Use.
Microsemi Corporation reserves the right to change products or specifications without notice.
October 2010
Rev. 6
© 2010 Microsemi Corporation. All rights reserved.
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3E64M72S-XSBX
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
WE
0
#
RAS
0
#
CAS
0
#
WE# RAS# CAS#
A
0-12
DQ
0
BA
0-1
WE# RAS# CAS#
A
0-12
DQ
0
BA
0-1
A
0-12
BA
0-1
DQ
0
DQ
8
CK
0
CK
0
#
CKE
0
CS
0
#
DQML
0
DQSL
0
WE
1
#
RAS
1
#
CAS
1
#
CK
CK#
CKE
CS#
DQML
IC0
DQ
7
DQ
7
CK
0
CK
0
#
CKE
0
CS
0
#
DQMH
0
DQSH
0
CK
CK#
CKE
CS#
DQM
IC5
DQ
7
DQ
15
WE# RAS# CAS#
A
0-12
BA
0-1
DQ
0
DQ
16
WE# RAS# CAS#
A
0-12
BA
0-1
DQ
0
DQ
24
CK
1
CK
1
#
CKE
1
CS
1
#
DQML
1
DQSL
1
WE
2
#
RAS
2
#
CAS
2
#
CK
CK#
CKE
CS#
DQM
IC1
CK
1
CK
1
#
CKE
1
CS
1
#
DQ
7
DQ
23
DQMH
1
DQSH
1
CK
CK#
CKE
CS#
DQM
IC6
DQ
7
DQ
31
WE# RAS# CAS#
A
0-12
BA
0-1
DQ
0
DQ
32
WE# RAS# CAS#
A
0-12
BA
0-1
DQ
0
DQ
40
CK
2
CK
2
#
CKE
2
CS
2
#
DQML
2
DQSL
2
WE
3
#
RAS
3
#
CAS
3
#
CK
CK#
CKE
CS#
DQM
IC2
DQ
7
DQ
39
CK
2
CK
2
#
CKE
2
CS
2
#
DQMH
2
DQSH
2
CK
CK#
CKE
CS#
DQM
IC7
DQ
7
DQ
47
WE# RAS# CAS#
A
0-12
BA
0-1
DQ
0
DQ
48
WE# RAS# CAS#
A
0-12
BA
0-1
DQ
0
DQ
56
CK
3
CK
3
#
CKE
3
CS
3
#
DQML
3
DQSL
3
WE
4
#
RAS
4
#
CAS
4
#
CK
CK#
CKE
CS#
DQM
IC3
DQ
7
DQ
55
CK
3
CK
3
#
CKE
3
CS
3
#
DQMH
3
DQSH
3
CK
CK#
CKE
CS#
DQM
IC8
DQ
7
DQ
63
WE# RAS# CAS#
A
0-12
DQ
0
BA
0-1
DQ
64
CK
4
CK
4
#
CKE
4
CS
4
#
DQML
4
DQSL
4
CK
CK#
CKE
CS#
DQM
IC4
DQ
7
DQ
71
Microsemi Corporation reserves the right to change products or specifications without notice.
October 2010
Rev. 6
© 2010 Microsemi Corporation. All rights reserved.
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3E64M72S-XSBX
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of operation
of the DDR SDRAM. This definition includes the selection of a
burst length, a burst type, a CAS latency, and an operating mode,
as shown in Figure 3. The Mode Register is programmed via the
MODE REGISTER SET command (with BA0 = 0 and BA1 = 0)
and will retain the stored information until it is programmed again
or the device loses power. (Except for bit A8 which is self clearing).
Reprogramming the mode register will not alter the contents of
the memory, provided it is performed correctly. The Mode Register
must be loaded (reloaded) when all banks are idle and no bursts
are in progress, and the controller must wait the speci
fi
ed time
before initiating the subsequent operation. Violating either of these
requirements will result in unspeci
fi
ed operation.
Mode register bits A0-A2 specify the burst length, A3 speci
fi
es the
type of burst (sequential or interleaved), A4-A6 specify the CAS
latency, and A7-A12 specify the operating mode.
If a READ command is registered at clock edge n, and the latency
is m clocks, the data will be available by clock edge n+m. Table
2 below indicates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to zero,
and bits A0-A6 set to the desired values. A DLL reset is initiated
by issuing a MODE REGISTER SET command with bits A7 and
A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to
the desired values. Although not required, JEDEC specifications
recommend when a LOAD MODE REGISTER command is issued
to reset the DLL, it should always be followed by a LOAD MODE
REGISTER command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future
use and/or test modes. Test modes and reserved states should
not be used because unknown operation or incompatibility with
future versions may result.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst oriented,
with the burst length being programmable, as shown in Figure
3. The burst length determines the maximum number of column
locations that can be accessed for a given READ or WRITE
command. Burst lengths of 2, 4 or 8 locations are available for
both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst will
wrap within the block if a boundary is reached. The block is uniquely
selected by A1-Ai when the burst length is set to two; by A2-Ai
when the burst length is set to four (where Ai is the most significant
column address for a given configuration); and by A3-Ai when
the burst length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to both READ
and WRITE bursts.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond those
controlled by the mode register; these additional functions are DLL
enable/disable, output drive strength, and QFC. These functions
are controlled via the bits shown in Figure 5. The extended mode
register is programmed via the LOAD MODE REGISTER command
to the mode register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the device loses
power. The enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode register (BA0/
BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when all banks are
idle and no bursts are in progress, and the controller must wait the
specified time before initiating any subsequent operation. Violating
either of these requirements could result in unspecified operation.
TABLE 2 – CAS LATENCY
ALLOWABLE OPERATING FREQUENCY (MHz)
SPEED
-200
-250
-266
-333 IND
-333 MIL
CAS LATENCY = 2
≤
75
≤
100
≤
100
≤
100
≤
100
CAS LATENCY = 2.5
≤
100
≤
125
≤
133
≤
166
≤
133
CAS LATENCY = 3
—
—
—
≤
166
≤
166
BURST TYPE
Accesses within a given burst may be programmed to be either
sequential or interleaved; this is referred to as the burst type and
is selected via bit M3.
The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address, as shown
in Table 1.
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specified to be
SSTL2, Class II. The DDR SDRAM supports an option for reduced
drive. This option is intended for the support of the lighter load
and/or point-to-point environments. The selection of the reduced
drive strength will alter the DQs and DQSs from SSTL2, Class II
READ LATENCY
The READ latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
fi
rst bit
of output data. The latency can be set to 2 or 2.5 clocks.
Microsemi Corporation reserves the right to change products or specifications without notice.
October 2010
Rev. 6
© 2010 Microsemi Corporation. All rights reserved.
5
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
Electronics Design Contest
京公网安备 11010802033920号
EEWORLD
