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AP164510
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AP164510.EXE
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Hardware I
2
C-bus in slave mode by using polling and
interrupt methods for C161RI microcontroller
This is a software module for hardware I
2
C-bus in slave mode by using software polling
and hardware interrupt methods for C161RI microcontroller. The I
2
C-bus is used in
many applications mainly to communicate between devices connected to the bus.
Author: Tan Choon Hock / SCPL HL SAC AP
Semiconductor Group
2.98, Rel. 01
Hardware I
2
C-bus in slave mode by using
polling and interrupt methods for C161RI
1
2
Introduction to I
2
C-bus .......................................................................................... 3
I
2
C-bus Specifications ........................................................................................... 3
2.1
2.2
2.3
Data Transfer Formats ................................................................................... 3
Timing Diagram.............................................................................................. 7
Hardware Connection .................................................................................... 9
3
Software Description............................................................................................ 10
3.1
Software Concept......................................................................................... 10
3.1.1 Software polling method .................................................................... 10
3.1.2 Hardware interrupt method................................................................ 11
Description of Module Subroutines .............................................................. 12
3.2.1 Software polling method .................................................................... 12
3.2.2 Hardware interrupt method................................................................ 13
3.2
4
Software Listing.................................................................................................... 14
4.1
4.2
Software polling method (SLAVE4.C) .......................................................... 14
Hardware interrupt method (SLAVE2.C) ...................................................... 17
AP164510 ApNote - Revision History
Actual Revision : Rel. 1.0
Previous Revison: none
Page of
Page of
actual Rel. prev. Rel.
Semiconductor Group
2
of 20
AP1645
2.98
Hardware I
2
C-bus in slave mode by using
polling and interrupt methods for C161RI
1
Introduction to I
2
C-bus
The I
2
C-bus or Inter-Integrated Circuit bus has been developed by Philips. it allows
integrated circuits to communicate directly with each other via a simple bi-directional 2-
wire bus. The two bus lines are serial clock line (SCL), and serial data line (SDA).
Nowadays, the I
2
C-bus becomes a standard bus system which is used in consumer
electronics, telecommunications, and industrial electronics.
This software module can support the multi-master operation for hardware I
2
C-bus in
slave mode. It is using the internal hardware peripheral of I
2
C-bus to receive clock, and
transmit or receive the data. The slave address can be configured to 7-bit addressing as
well as 10-bit addressing. It can support the clock frequency of the I
2
C -bus up to 400 KHz
with 16 MHz CPU of the C161RI microcontroller.
2
2.1
I
2
C-bus Specifications
Data Transfer formats
A HIGH-to-LOW transition of the data line (SDA) while the clock line (SCL) is HIGH
indicates a START condition. A LOW-to-HIGH transition of the SDA while SCL is HIGH
defines a STOP condition. The data line can only be changed when the clock signal on the
SCL line is LOW. Therefore, the data on the SDA line must be stable during the HIGH
period of the clock signal. The bus is considered to be busy after the START condition and
is considered to be free at a certain time interval after the STOP condition.
Each information puts on the SDA line must be 8-bit long. The data is transferred serially
with the most significant bit first, and followed by an acknowledge bit. The 9th clock pulse
of the acknowledge bit is generated by the master. The transmitting device has to release
the SDA line (HIGH or in the high impedance state) during this clock pulse while the
device that needs to acknowledge has to pull down the SDA line during this clock pulse.
The number of data bytes transferred between the START and STOP condition from the
transmitter and receiver is not limited.
The receiver is obliged to generate an acknowledge bit after each byte of data that has
been received. When the receiver does not provide an acknowledge bit after having
received a byte of data, the data line must be left HIGH or in the high impedance state by
the slave. The master can then generate a STOP condition to abort the transfer. One of
the reason for the receiver not to provide the acknowledge bit is that the receiver is
performing some real-time function. If the master is receiving data, it must signal the end
of the data to the slave by not generating an acknowledge bit on the last byte of data
received. Then, the slave must release the data line to allow the master to generate the
STOP condition.
Semiconductor Group
3
of 20
AP1645
2.98
Hardware I
2
C-bus in slave mode by using
polling and interrupt methods for C161RI
A complete data transfer format is shown in Figure 1. After a START condition, a slave
address is sent. The address is 7 bits long followed by an 8th bit which is a data direction
bit (R/W). A „ for data direction bit indicates a transmission (WRITE), and a „ indicates
0“
1“
2
a request for data (READ). Figure 2 shows the I C-bus data transfer format of writing data
from master to slave device. Figure 3 shows the data transfer format of reading data from
the slave device.
A data transfer is always terminated by STOP condition generated by the master.
However, if the master still wishes to communicate on the bus, it can generate a repeated
START condition and address the same device or another slave device without first
generating a STOP condition. This combined data transfer format is shown in figure 4.
SCL
1-7
SDA
8
9
1-7
8
9
1-7
8
9
Start
Condition
Address
R/W
Ack
R/W
A
Data
Data
Ack
A
Data
Data
Ack
A/NA
Stop
Condition
S
Slave Address
P
Start-Frame
Read- or Write-Frame
Stop-Frame
Transfer-Frame
from master to slave.
from master to slave or
form slave to master depends
of the R/W bit.
from slave to master.
A/NA = Acknowledge.(SDA = LOW)
or not acknowledge(SDA = HIGH) if it is the last data to be read by master.
Figure 1:
A complete data transfer format of I
2
C-bus
Semiconductor Group
4
of 20
AP1645
2.98
Hardware I
2
C-bus in slave mode by using
polling and interrupt methods for C161RI
S
Slave Address
R/W
A
Data
A
Data
A
P
Data transfer
(n bytes + acknowledge)
0 (WRITE)
From master to slave.
From slave to master.
Figure 2:
I
2
C-bus data transfer format of writing data to slave
S
Slave Address
R/W
A
Data
A
Data
NA
P
Data transfer
(n bytes + aknowledge)
1 (READ)
From master to slave.
From slave to master.
NA -- not acknowledge for the last data to be received. (SDA = HIGH)
Figure 3:
I
2
C-bus data transfer format of reading data from slave
Semiconductor Group
5
of 20
AP1645
2.98
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