SAF-C161RI-LF datasheet, PDF - EEWORLD Datasheet

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SAF-C161RI-LF: DescriptionMicrocontroller, 16-Bit, 80166 CPU, 20MHz, CMOS, PQFP100, METRIC, PLASTIC, TQFP-100; CategoryThe embedded processor and controller Microcontrollers and processors; File Size119KB，20 Pages; ManufacturerInfineon; Websitehttp://www.infineon.com/

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SAF-C161RI-LF Overview

Microcontroller, 16-Bit, 80166 CPU, 20MHz, CMOS, PQFP100, METRIC, PLASTIC, TQFP-100

SAF-C161RI-LF Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Infineon
Parts packaging code	QFP
package instruction	METRIC, PLASTIC, TQFP-100
Contacts	100
Reach Compliance Code	unknown
ECCN code	3A991.A.2
Has ADC	YES
Address bus width	23
bit size	16
CPU series	80166
maximum clock frequency	32.2 MHz
DAC channel	NO
DMA channel	NO
External data bus width	16
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
Number of I/O lines	76
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	1024
rom(word)	0
Maximum seat height	1.6 mm
speed	20 MHz
Maximum slew rate	55 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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Microcontrollers

ApNote

AP164510

additional file

AP164510.EXE

available

Hardware I

C-bus in slave mode by using polling and

interrupt methods for C161RI microcontroller

This is a software module for hardware I

C-bus in slave mode by using software polling

and hardware interrupt methods for C161RI microcontroller. The I

C-bus is used in

many applications mainly to communicate between devices connected to the bus.

Author: Tan Choon Hock / SCPL HL SAC AP

Semiconductor Group

2.98, Rel. 01

Hardware I

C-bus in slave mode by using

polling and interrupt methods for C161RI

Introduction to I

C-bus

The I

C-bus or Inter-Integrated Circuit bus has been developed by Philips. it allows

integrated circuits to communicate directly with each other via a simple bi-directional 2-

wire bus. The two bus lines are serial clock line (SCL), and serial data line (SDA).

Nowadays, the I

C-bus becomes a standard bus system which is used in consumer

electronics, telecommunications, and industrial electronics.

This software module can support the multi-master operation for hardware I

C-bus in

slave mode. It is using the internal hardware peripheral of I

C-bus to receive clock, and

transmit or receive the data. The slave address can be configured to 7-bit addressing as

well as 10-bit addressing. It can support the clock frequency of the I

C -bus up to 400 KHz

with 16 MHz CPU of the C161RI microcontroller.

2.1

C-bus Specifications

Data Transfer formats

A HIGH-to-LOW transition of the data line (SDA) while the clock line (SCL) is HIGH

indicates a START condition. A LOW-to-HIGH transition of the SDA while SCL is HIGH

defines a STOP condition. The data line can only be changed when the clock signal on the

SCL line is LOW. Therefore, the data on the SDA line must be stable during the HIGH

period of the clock signal. The bus is considered to be busy after the START condition and

is considered to be free at a certain time interval after the STOP condition.

Each information puts on the SDA line must be 8-bit long. The data is transferred serially

with the most significant bit first, and followed by an acknowledge bit. The 9th clock pulse

of the acknowledge bit is generated by the master. The transmitting device has to release

the SDA line (HIGH or in the high impedance state) during this clock pulse while the

device that needs to acknowledge has to pull down the SDA line during this clock pulse.

The number of data bytes transferred between the START and STOP condition from the

transmitter and receiver is not limited.

The receiver is obliged to generate an acknowledge bit after each byte of data that has

been received. When the receiver does not provide an acknowledge bit after having

received a byte of data, the data line must be left HIGH or in the high impedance state by

the slave. The master can then generate a STOP condition to abort the transfer. One of

the reason for the receiver not to provide the acknowledge bit is that the receiver is

performing some real-time function. If the master is receiving data, it must signal the end

of the data to the slave by not generating an acknowledge bit on the last byte of data

received. Then, the slave must release the data line to allow the master to generate the

STOP condition.

Semiconductor Group

of 20

AP1645

2.98

SAF-C161RI-LF Related Products

	SAF-C161RI-LF	SAB-C161RI-LF
Description	Microcontroller, 16-Bit, 80166 CPU, 20MHz, CMOS, PQFP100, METRIC, PLASTIC, TQFP-100	Microcontroller, 16-Bit, 80166 CPU, 20MHz, CMOS, PQFP100, METRIC, PLASTIC, TQFP-100
Is it Rohs certified?	incompatible	incompatible
Maker	Infineon	Infineon
Parts packaging code	QFP	QFP
package instruction	METRIC, PLASTIC, TQFP-100	METRIC, PLASTIC, TQFP-100
Contacts	100	100
Reach Compliance Code	unknown	unknown
ECCN code	3A991.A.2	3A991.A.2
Has ADC	YES	YES
Address bus width	23	23
bit size	16	16
CPU series	80166	80166
maximum clock frequency	32.2 MHz	32.2 MHz
DAC channel	NO	NO
DMA channel	NO	NO
External data bus width	16	16
JESD-30 code	S-PQFP-G100	S-PQFP-G100
JESD-609 code	e0	e0
length	14 mm	14 mm
Number of I/O lines	76	76
Number of terminals	100	100
Maximum operating temperature	85 °C	70 °C
PWM channel	YES	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20	QFP100,.63SQ,20
Package shape	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V
Certification status	Not Qualified	Not Qualified
RAM (bytes)	1024	1024
Maximum seat height	1.6 mm	1.6 mm
speed	20 MHz	20 MHz
Maximum slew rate	55 mA	55 mA
Maximum supply voltage	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	14 mm	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER	MICROCONTROLLER
Base Number Matches	1	1

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