CS1087
Vacuum Fluorescent
Display Tube Driver
The VFD Driver is a microprocessor interface IC that drives a
multiplexed VF (Vacuum Fluorescent) display tube. It consists of a
32–bit shift register, a 32–bit transparent data latch, a metal mask
ROM, six 20 mA anode output drivers, twenty–three 2 mA anode
output drivers, and three 50 mA grid drivers with output enables.
Features
•
Power On Reset
•
Display Dimming Possible
•
Three, 50 mA Grid Drivers
•
Anode Options – DIP–40 and PCLL–44:
–
6 @ 20 mA
–
23 @ 2 mA
•
Anode Options – SO–28L:
–
3 @ 20 mA
–
15 @ 2 mA
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40
1
DIP–40
WIDE BODY
N SUFFIX
CASE 711
PLCC–44
FN SUFFIX
CASE 777
28
Chip Select
V
IGN
12 V
Clock
SO–28L
DW SUFFIX
CASE 751F
1
ORDERING INFORMATION*
Data Out
SPI Functions
Regulator
5V
GND
Device
CS1087XN40
Package
DIP–40
WIDE BODY
PLCC–44
PLCC–44
SO–28L
SO–28L
Shipping
9 Units/Rail
23 Units/Rail
500 Tape & Reel
27 Units/Rail
1000 Tape & Reel
Anodes
1:29
0.1
µF
V
CC
µP
PORT
PORT
PORT
GND PORT
V
BB
FILAMENT
VFD
GRID1GRID2 GRID3 GND
CS1087XFN44
CS1087XFNR44
CS1087XDW28
CS1087XDWR28
V
BAT
CS1087
D
OUT
D
IN
GRID1
CLK GRID2
STB GRID3
GREN
GND
*For additional package options, consult your local
ON Semiconductor sales office.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
Figure 1. Application Diagram
©
Semiconductor Components Industries, LLC, 2001
1
August, 2001 – Rev. 11
Publication Order Number:
CS1087/D
CS1087
MAXIMUM RATINGS*
Parameter
Supply Voltage (V
BB
)
Input Voltages (D
IN
, CLK, STB, GREN)
Junction Temperature Range
Storage Temperature Range
ESD Susceptibility (Human Body Model)
ESD Susceptibility (Machine Model)
Package Thermal Resistance, DIP–40
Junction–to–Case, R
θJC
Junction–to–Ambient, R
θJA
Package Thermal Resistance, PLCC–44
Junction–to–Case, R
θJC
Junction–to–Ambient, R
θJA
Package Thermal Resistance, SO–28L
Junction–to–Case, R
θJC
Junction–to–Ambient, R
θJA
Lead Temperature Soldering:
1. 10 second maximum.
2. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
Wave Solder (through hole styles only) Note 1
Reflow (SMD styles only) Note 2
Value
–0.6 to +18
–0.6 to +6.0
–40 to +150
–55 to +150
2.0
200
20
45
16
55
15
75
260 Peak
230 Peak
Unit
V
V
°C
°C
kV
V
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS
(8.0 V
≤
V
BB
≤
16.5 V, Gnd = 0 V, –40°C
≤
T
J
≤
105°C; unless otherwise stated. Note 3.)
Parameter
V
BB
Input
V
BB
Input Voltage
I
BB0
Current
Reset Mode
D
IN
, CLK, STB Inputs
V
IL1
, Input Low Voltage
V
IH
, Input High Voltage
I
IL
, Input Current
GREN Input
V
IL
, Input Low Voltage
V
IH
, Input High Voltage
I
IH
, Input Pull–down Current
GRID1, GRID2, GRID3 Outputs
I
OL
I
OH
V
OL
V
OH
Sink Current
Source Current
I
OUT
= 1.0 mA
I
OUT
= –50 mA, V
BB
= 12 V
1.0
50
–
V
BB
– 0.75
–
–
–
–
–
–
0.5
V
BB
mA
mA
V
V
V
IN
= 3.325 V
–
–
–
3.3
–
–
–
30
1.6
–
60
V
V
µA
V
IN
= V
IH
–
–
–
3.3
–
–
–
7.5
1.6
–
20.0
V
V
µA
–
No outputs active, V
BB
= 16.5 V
All outputs forced low.
8.0
–
–
–
2.0
6.5
16.5
5.0
7.5
V
mA
V
Test Conditions
Min
Typ
Max
Unit
3. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested
in production.
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2
CS1087
ELECTRICAL CHARACTERISTICS (continued)
(8.0 V
≤
V
BB
≤
16.5 V, Gnd = 0 V, –40°C
≤
T
J
≤
105°C; unless otherwise stated.
Note 4.)
Parameter
AN24 – AN29 Outputs
I
OL
I
OH
V
OL
V
OH
AN1 – AN23 Outputs
I
OL
I
OH
V
OL
V
OH
D
OUT
Output
I
OL
I
OH
V
OL
V
OH
Sink Current
Source Current
I
OUT
= 1.0 mA
I
OUT
= –1.0 mA
1.0
1.0
–
3.9
–
–
–
–
–
–
0.5
5.1
mA
mA
V
V
Sink Current
Source Current
I
OUT
= 100
µA
I
OUT
= –2.0 mA, V
BB
= 12 V
100
2.0
–
V
BB
– 0.5
–
–
–
–
–
–
0.5
V
BB
µA
mA
V
V
Sink Current
Source Current
I
OUT
= 400
µA
I
OUT
= –20 mA, V
BB
= 12 V
400
20
–
V
BB
– 0.5
–
–
–
–
–
–
0.5
V
BB
µA
mA
V
V
Test Conditions
Min
Typ
Max
Unit
AC Characteristics: Input and Output Timing
F
C
, CLK Frequency
T
CL
, CLK Low Time
T
CH
, CLK High Time
T
CR
, CLK Rise Time
T
CF
, CLK Fall Time
T
CD
, CLK Low to D
OUT
Propagation Delay
T
SC
, STB Low to CLK High Time
T
ST
, STB High Time
T
AN
, STB High to Anode Output
Propagation Delay
T
GL
, Grid Turn On Propagation Delay
T
G0
, Grid Turn Off Propagation Delay
T
GR
, Grid Rise Time
T
GF
, Grid Fall Time
T
AR
, Anode Rise Time
T
AF
, Anode Fall Time
V
BB
= 12 V
V
BB
= 12 V
At rated load. Note 5.
At rated load. Note 5.
At rated load. Note 5.
At rated load. Note 5.
–
–
–
–
–
–
–
–
–
0
200
200
–
–
–
50
500
–
–
–
0.50
0.35
0.40
0.40
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.0
–
–
100
100
200
–
–
5.0
2.0
5.0
2.00
2.00
2.00
2.50
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
4. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested
in production.
5. Grid and anode rise/fall times are measured from 10% and 90% points. Output currents are at the maximum rated currents for the
respective stages.
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CS1087
PACKAGE LEAD DESCRIPTION
Package Lead Number
40L DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
44L PLCC
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
2
3
4
5
6
7
8
9
10
1, 11, 12, 23, 34
13
SO–28L
1
2
3
–
4
5
6
–
7
–
–
8
–
9
10
11
12
13
–
14
15
–
16
17
18
19
–
20
21
22
–
–
–
23
24
25
26
27
–
28
Lead Symbol
(29 Anode Configuration)
GRID1
GRID2
GRID3
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
GND
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
D
OUT
D
IN
CLK
STB
GREN
NC
V
BB
50 mA grid output.
50 mA grid output.
50 mA grid output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
Ground connection.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
2.0 mA anode output.
20 mA anode output.
20 mA anode output.
20 mA anode output.
20 mA anode output.
20 mA anode output.
20 mA anode output.
Shift register data output.
Shift register data input.
Shift register clock input.
Transfer contents of shift registers to output stages.
Grid outputs enable.
No connection.
Supply voltage input.
Function
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CS1087
GRID1 GRID2 GRID3
AN1
AN2
AN3
AN23
AN24
AN25
AN26
AN27
AN28
AN29
V
BB
V
REG
POR
GND
V
REG
V
REG
GREN
V
REG
METAL MASK ROM
STB
D Q
V
REG
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
V
REG
D
IN
D Q
CLK
V
REG
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D
OUT
CLK
Output Drive Capability
Grid Outputs: 50 mA
AN24–AN29: 20 mA
AN1–AN23: 2.0 mA
Figure 2. Block Diagram
OPERATION DESCRIPTION
Upon the initial application of power, the power on reset
function will cause all of the anode and grid driver outputs
to be off and all shift register outputs to be set low. Data is
fed into the shift register through the D
IN
pin at the rising
edge of the CLK input. Thirty two bits of data are capable of
being stored by the shift register. Once the desired pattern is
stored in the shift register, it can be transferred to the latch
by setting the STB input high. The output of each latch
drives its corresponding output stage. A logic high input to
the shift register/latch will cause the corresponding output
to turn on. A logic low input to the shift register/latch will
cause the corresponding output to turn off. Please note that
if the STB is held high, the outputs of the latch reflect the
outputs of the corresponding shift register bits and will
change if data is shifted in.
The three GRID outputs are gated by the GREN input.
When GREN is low, the GRID outputs are forced low
regardless of the state of the corresponding latch output.
When GREN is high, the GRID outputs correspond to the
state of their respective latch outputs. The anode outputs,
AN1 to AN29 are always enabled.
The D
OUT
pin is the output of the last stage of the shift
register to allow serial cascading of this IC with other
devices. Data from the last stage of the shift register is
supplied to the D
OUT
pin delayed by 1/2 CLK cycle. Data on
the D
OUT
output changes with the falling edges of the CLK
to prevent logic race conditions between the CLK and the
D
IN
of the next IC in the serial chain.
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