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FN9062
Rev 2.00
Apr 13, 2004
ISL6504, ISL6504A
Multiple Linear Power Controller with ACPI Control Interface
The ISL6504 and ISL6504A complement other power
building blocks (voltage regulators) in ACPI-compliant
designs for microprocessor and computer applications. The
IC integrates three linear controllers/regulators, switching,
monitoring and control functions into a 16-pin wide-body
SOIC or 20-pin QFN 6x6 package. The ISL6504, ISL6504A
operating mode (active outputs or sleep outputs) is
selectable through two digital control pins, S3 and S5.
One linear controller generates the 3.3V
DUAL
/3.3V
SB
voltage plane from the ATX supply’s 5V
SB
output, powering
the south bridge and the PCI slots through an external NPN
pass transistor during sleep states (S3, S4/S5). In active
state (during S0 and S1/S2), the 3.3V
DUAL
/3.3V
SB
linear
regulator uses an external N-channel pass MOSFET to
connect the outputs directly to the 3.3V input supplied by an
ATX power supply, for minimal losses.
A controller powers up the 5V
DUAL
plane by switching in the
ATX 5V output through an NMOS transistor in active states,
or by switching in the ATX 5V
SB
through a PMOS (or PNP)
transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6504 5V
DUAL
output is shut down. In the ISL6504A, the
5V
DUAL
output stays on during S4/S5 sleep states. This is
the only difference between the two parts; see Table 1.
An internal linear regulator supplies the 1.2V for the voltage
identification circuitry (VID) only during active states (S0 and
S1/S2), and uses the 3V3 pin as input source for its internal
pass element. Another internal regulator outputs a 1.5V
SB
chip-set standby supply, which uses the 3V3DL pin as input
source for its internal pass element. The 3.3V
DUAL
/3.3V
SB
and 1.5V
SB
outputs are active for as long as the ATX 5V
SB
voltage is applied to the chip.
Features
• Provides four ACPI-Controlled Voltages
- 5V
DUAL
USB/Keyboard/Mouse
- 3.3V
DUAL
/3.3V
SB
PCI/Auxiliary/LAN
- 1.2V
VID
Processor VID Circuitry
- 1.5V
SB
ICH4 Resume Well
• Excellent Output Voltage Regulation
- All Outputs:
2.0%
over temperature (as applicable)
• Small Size; Very Low External Component Count
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
• QFN Package:
- Near Chip Scale Package Footprint; Improved PCB
Efficiency; Thinner profile
• Pb-Free Available (RoHS Compliant)
Applications
• ACPI-Compliant Power Regulation for Motherboards
- ISL6504: 5V
DUAL
is shut down in S4/S5 sleep states
- ISL6504A: 5V
DUAL
stays on in S4/S5 sleep states
FN9062 Rev 2.00
Apr 13, 2004
Page 1 of 17
ISL6504, ISL6504A
Pinouts
ISL6504/A (WIDE BODY SOIC)
TOP VIEW
1V5SB
1
16 5VSB
15 VID_CT
14 VID_PG
13 SS
12 5VDL
11 5VDLSB
10 DLA
9
FAULT
Ordering Information
PART NUMBER
ISL6504CB
ISL6504CBZ
(Note)
ISL6504CBN
ISL6504CBNZ
(Note)
ISL6504CR
ISL6504CRZ
(Note)
ISL6504EVAL1
ISL6504ACB
ISL6504ACBZ
(Note)
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
16 Ld SOIC
16 Ld SOIC
(Pb-free)
16 Ld SOIC
16 Ld SOIC
(Pb-free)
20 Ld 6x6 QFN
20 Ld 6x6 QFN
(Pb-free)
PKG.
DWG. #
M16.3
M16.3
M16.15
M16.15
L20.6x6
L20.6x6
3V3DLSB 2
3V3DL 3
1V2VID 4
3V3 5
S3
S5
6
7
GND 8
NOTE: SOIC layout should accomodate both wide and narrow footprints.
ISL6504/A (6
X
6 QFN)
TOP VIEW
3V3DLSB
VID_CT
1V5SB
5VSB
Evaluation Board
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
16 Ld SOIC
16 Ld SOIC
(Pb-free)
16 Ld SOIC
16 Ld SOIC
(Pb-free)
20 Ld 6x6 QFN
20 Ld 6x6 QFN
(Pb-free)
M16.3
M16.3
M16.15
M16.15
L20.6x6
L20.6x6
20
3V3DL
NC
1V2VID
3V3
S3
1
2
3
4
5
6
NC
19
18
NC
17
16
15 VID_PG
14 SS
13 NC
12 5VDL
11 5VDLSB
ISL6504ACBN
ISL6504ACBNZ
(Note)
ISL6504ACR
ISL6504ACRZ
(Note)
ISL6504AEVAL1
7
S5
8
GND
9
FAULT
10
DLA
Evaluation Board
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
NOTE: The QFN bottom pad is electrically connected to the IC substrate, at
GND potential. It can be left unconnected, or connected to GND; do NOT
connect to another potential.
FN9062 Rev 2.00
Apr 13, 2004
Page 2 of 17
ISL6504, ISL6504A
Absolute Maximum Ratings
Supply Voltage, V
5VSB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V
ESD Classification (Human Body Model) . . . . . . . . . . . . . . . . . .2kV
Thermal Information
Thermal Resistance (Typical)
JA
(
o
C/W)
JC
(
o
C/W)
Recommended Operating Conditions
Supply Voltage, V
5VSB
. . . . . . . . . . . . . . . . . . . . . . . . . . . +5V
5%
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, V
Sx
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +5.5V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0
o
C to 125
o
C
SOIC Package (Note 1) . . . . . . . . . . .
70
N/A
QFN Package (Note 2) . . . . . . . . . . . .
32
4.0
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
JC,
the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply Current
Shutdown Supply Current
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
5VSB
I
5VSB(OFF)
V
SS
= 0.8V
-
-
17
4
-
-
mA
mA
POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS
Rising 5VSB POR Threshold
5VSB POR Hysteresis
Rising 3V3 Threshold
3V3 Hysteresis
Falling Threshold Timeout (All Monitors)
Soft-Start Current
Shutdown Voltage Threshold
VID_PG Rising Threshold
VID_PG Hysteresis
1.5V
SB
LINEAR REGULATOR (V
OUT1
)
Regulation
1V5SB Nominal Voltage Level
1V5SB Undervoltage Rising Threshold
1V5SB Undervoltage Hysteresis
1V5SB Output Current
1.2V
VID
LINEAR REGULATOR (V
OUT2
)
Regulation
1V2VID Nominal Voltage Level
1V2VID Undervoltage Rising Threshold
1V2VID Undervoltage Hysteresis
1V2VID Output Current
I
1V2VID
V
3V3
= 3.3V
V
1V2VID
-
-
-
-
40
-
1.2
0.96
60
-
2.0
-
-
-
-
%
V
V
mV
mA
I
1V5SB
V
3V3DL
= 3.3V
V
1V5SB
-
-
-
-
85
-
1.5
1.25
75
-
2.0
-
-
-
-
%
V
V
mV
mA
I
SS
V
SD
-
-
-
-
-
-
-
-
-
-
0.9
2.75
150
10
10
-
1.02
56
4.5
-
-
-
-
-
0.8
-
-
V
V
V
mV
s
A
V
V
mV
FN9062 Rev 2.00
Apr 13, 2004
Page 5 of 17
Industrial Control Electronics
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