Integrated
Circuit
Systems, Inc.
ICS8430I-61
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
Dual differential 3.3V LVPECL outputs
•
Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
•
Output frequency range: 20.83MHz to 500MHz
•
Crystal input frequency range: 14MHz to 27MHz
•
VCO range: 250MHz to 500MHz
•
Parallel or serial interface for programming counter
and output dividers
•
RMS period jitter: 6ps (maximum)
•
Cycle-to-cycle jitter: 30ps (maximum)
•
Supply voltage modes:
3.3/3.3/3.3
3.3/3.3/2.5
•
-40°C to 85°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8430I-61 is a general purpose, dual output
Crystal-to-3.3V Differential LVPECL High Fre-
HiPerClockS™
quency Synthesizer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8430I-61 has a select-
able TEST_CLK or crystal inputs. The VCO operates at a fre-
quency range of 250MHz to 500MHz. The VCO frequency is
programmed in steps equal to the value of the input reference
or crystal frequency. The VCO and output frequency can be
programmed using the serial or parallel interfaces to the con-
figuration logic. Frequency steps as small as 1MHz can be
achieved using a 16MHz crystal or TEST_CLK.
ICS
B
LOCK
D
IAGRAM
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
OSC
XTAL_OUT
÷
16
P
IN
A
SSIGNMENT
XTAL_OUT
VCO_SEL
nP_LOAD
M4
M3
M2
M1
M0
0
32 31 30 29 28 27 26 25
1
M5
M6
M7
÷1
÷1.5
÷2
÷3
÷4
÷6
÷8
÷12
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
V
CC
FOUT1
nFOUT1
V
CCO
FOUT0
nFOUT0
V
EE
24
23
22
XTAL_IN
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
M8
N0
N1
N2
FOUT0
nFOUT0
FOUT1
nFOUT1
ICS8430I-61
21
20
19
18
17
PLL
PHASE DETECTOR
MR
VCO
÷
M
0
1
V
EE
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N2
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8430AYI-61
www.icst.com/products/hiperclocks.html
1
REV. A OCTOBER 21, 2004
Integrated
Circuit
Systems, Inc.
ICS8430I-61
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
specific default state that will automatically occur during
power-up. The TEST output is LOW when operating in the
parallel input mode. The relationship between the VCO fre-
quency, the crystal frequency and the M divider is defined as
follows: fVCO = fxtal x M
16
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
16MHz reference are defined as 250
≤
M
≤
500. The frequency
out is defined as follows: fout = fVCO = fxtal x M
N
N
16
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS8430I-61 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A parallel-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crys-
tal, this provides a 1MHz reference frequency. The VCO of
the PLL operates over a range of 250MHz to 500MHz. The
output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (ei-
ther too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the ICS8430I-61 support two
input modes and to program the M divider and N output di-
vider. The two input operational modes are parallel and serial.
Figure 1
shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on inputs
M0 through M8 and N0 through N2 is passed directly to the M
divider and N output divider. On the LOW-to-HIGH transition
of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and N bits can
be hard-wired to set the M divider and N output divider to a
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data, Shift Register Input
Output of M divider
CMOS Fout
S
ERIAL
L
OADING
S_CLOCK
S_DATA
S_LOAD
T1
t
S
T0
H
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N2
nP_LOAD
M, N
t
S
t
H
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
8430AYI-61
www.icst.com/products/hiperclocks.html
2
REV. A OCTOBER 21, 2004
Integrated
Circuit
Systems, Inc.
ICS8430I-61
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
Type
Input
Input
Input
Input
Power
Output
Power
Output
Power
Output
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
28, 29, 30
31, 32, 1, 2
3, 4
5, 7
6
8, 16
9
10
11, 12
13
14, 15
Name
M0, M1, M2
M3, M4, M5, M6
M7, M8
N0, N2
N1
V
EE
TEST
V
CC
FOUT1, nFOUT1
V
CCO
FOUT0, nFOUT0
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of
nP_LOAD input. LVCMOS / LVTTL interface levels.
Pullup
Pulldown Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
Pullup
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS interface levels.
Core supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Output supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inver ted
outputs nFOUTx to go high. When Logic LOW, the internal dividers
and the outputs are enabled. Asser tion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Selects between cr ystal oscillator or test inputs as the PLL
reference source. Selects XTAL inputs when HIGH. Selects
TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
Test clock input. LVCMOS / LVTTL interface levels.
Cr ystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is
loaded into M divider, and when data present at N2:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
17
MR
Input
Pulldown
18
19
20
21
22
23
24,
25
26
27
S_CLOCK
S_DATA
S_LOAD
V
CCA
XTAL_SEL
TEST_CLK
XTAL_IN,
XTAL_OUT
nP_LOAD
VCO_SEL
Input
Input
Input
Power
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
8430AYI-61
www.icst.com/products/hiperclocks.html
3
REV. A OCTOBER 21, 2004
Integrated
Circuit
Systems, Inc.
ICS8430I-61
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
Conditions
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
X
X
L
L
↑
↓
L
H
MR
H
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
M
X
Data
Data
X
X
X
X
N
X
Data
Data
X
X
X
X
S_LOAD
L
H
X
X
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
(NOTE 1)
VCO Frequency
(MHz)
250
251
252
253
•
•
498
499
500
M Divide
250
251
252
253
•
•
498
499
500
256
M8
0
0
0
0
•
•
1
1
1
128
M7
1
1
1
1
•
•
1
1
1
64
M6
1
1
1
1
•
•
1
1
1
32
M5
1
1
1
1
•
•
1
1
1
16
M4
1
1
1
1
•
•
1
1
1
8
M3
1
1
1
1
•
•
0
0
0
4
M2
0
0
1
1
•
•
0
0
1
2
M1
1
1
0
0
•
•
1
1
0
1
M0
0
1
0
1
•
•
0
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to a TEST_CLK or crystal frequency of 16MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N2
0
0
0
0
1
1
1
1
8430AYI-61
N1
0
0
1
1
0
0
1
1
N0
0
1
0
1
0
1
0
1
N Divider Value
1
1.5
2
3
4
6
8
12
Output Frequency (MHz)
Minimum
250
166.66
12 5
83.33
62.5
41.66
31.25
20.83
Maximum
500
333.33
250
166.66
125
83.33
62.5
41.66
REV. A OCTOBER 21, 2004
www.icst.com/products/hiperclocks.html
4
Integrated
Circuit
Systems, Inc.
ICS8430I-61
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
155
55
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
Parameter
M0:M8, N0:N2, MR,
S_LOAD, S_DATA,
S_CLOCK, nP_LOAD,
VCO_SEL, XTAL_SEL
TEST_CLK
M0:M8, N0:N2, MR,
S_LOAD, S_DATA,
S_CLOCK, nP_LOAD,
VCO_SEL, XTAL_SEL
TEST_CLK
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
M5, XTAL_SEL, VCO_SEL
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
M5, XTAL_SEL, VCO_SEL
V
OH
V
OL
Output
High Voltage
Output
Low Voltage
TEST; NOTE 1
TEST; NOTE 1
Test Conditions
Minimu-
m
2
2
-0.3
-0.3
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V,
V
IN
= 0V
V
CC
= 3.465V,
V
IN
= 0V
-5
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
1.3
150
5
Units
V
V
V
V
µA
µA
µA
V
IH
Input
High Voltage
V
IL
Input
Low Voltage
I
IH
Input
High Current
I
IL
Input
Low Current
-150
2.6
0.5
µA
V
V
NOTE 1: Outputs terminated with 50Ω to V
CCO
/2.
8430AYI-61
www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 21, 2004
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