HD6473337YCP16 datasheet, PDF - EEWORLD Datasheet

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HD6473337YCP16: DescriptionMicrocontroller, 8-Bit, OTPROM, H8/300 CPU, 16MHz, CMOS, PQCC84, PLASTIC, LCC-84; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，642 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HD6473337YCP16 Overview

Microcontroller, 8-Bit, OTPROM, H8/300 CPU, 16MHz, CMOS, PQCC84, PLASTIC, LCC-84

HD6473337YCP16 Parametric

Parameter Name	Attribute value
Maker	Hitachi （Renesas ）
Parts packaging code	LCC
package instruction	QCCJ, LDCC84,1.2SQ
Contacts	84
Reach Compliance Code	unknown
Has ADC	YES
Address bus width	16
bit size	8
CPU series	H8/300
maximum clock frequency	16 MHz
DAC channel	YES
DMA channel	NO
External data bus width	8
JESD-30 code	S-PQCC-J84
length	29.28 mm
Number of I/O lines	66
Number of terminals	84
Maximum operating temperature	75 °C
Minimum operating temperature	-20 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC84,1.2SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	2048
rom(word)	61440
ROM programmability	OTPROM
Maximum seat height	4.6 mm
speed	16 MHz
Maximum slew rate	60 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	29.28 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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Hitachi Single-Chip Microcomputer

H8/3397 Series

H8/3397

HD6433397

H8/3396

HD6433396

H8/3394

HD6433394

H8/3337 Series

H8/3337Y

HD6473337Y, HD6433337Y

H8/3336Y

HD6433336Y

H8/3334Y

HD6473334Y, HD6433334Y

H8/3334YF-ZTAT™

HD64F3334Y

H8/3337YF-ZTAT™

HD64F3337Y

Hardware Manual

ADE-602-078B

Contents

Section 1

1.1

1.2

1.3

Overview

.....................................................................................................

Overview ........................................................................................................................

Block Diagram................................................................................................................

Pin Assignments and Functions......................................................................................

1.3.1

Pin Arrangement.............................................................................................

1.3.2

Pin Functions ..................................................................................................

Section 2

2.1

CPU

............................................................................................................... 25

2.2

2.3

2.4

2.5

2.6

2.7

Overview ........................................................................................................................

2.1.1

Features...........................................................................................................

2.1.2

Address Space.................................................................................................

2.1.3

Register Descriptions......................................................................................................

2.2.1

General Registers............................................................................................

2.2.2

Control Registers ............................................................................................

2.2.3

Initial Register Values ....................................................................................

Data Formats...................................................................................................................

2.3.1

Data Formats in General Registers .................................................................

2.3.2

Memory Data Formats....................................................................................

Addressing Modes ..........................................................................................................

2.4.1

Addressing Mode............................................................................................

2.4.2

Calculation of Effective Address....................................................................

Instruction Set.................................................................................................................

2.5.1

Data Transfer Instructions ..............................................................................

2.5.2

Arithmetic Operations ....................................................................................

2.5.3

Logic Operations ............................................................................................

2.5.4

Shift Operations ..............................................................................................

2.5.5

Bit Manipulations ...........................................................................................

2.5.6

Branching Instructions....................................................................................

2.5.7

System Control Instructions ...........................................................................

2.5.8

Block Data Transfer Instruction .....................................................................

CPU States ......................................................................................................................

2.6.1

Overview.........................................................................................................

2.6.2

Program Execution State ................................................................................

2.6.3

Exception-Handling State...............................................................................

2.6.4

Power-Down State ..........................................................................................

Access Timing and Bus Cycle........................................................................................

2.7.1

Access to On-Chip Memory (RAM and ROM) .............................................

2.7.2

Access to On-Chip Supporting Modules and External Devices.....................

Section 3

3.1

MCU Operating Modes and Address Space

..................................... 61

3.2

3.3

3.4

Overview ........................................................................................................................

3.1.1

Mode Selection ...............................................................................................

3.1.2

Mode and System Control Registers .............................................................

System Control Register (SYSCR).................................................................................

Mode Control Register (MDCR) ....................................................................................

Address Space Map in Each Operating Mode................................................................

Section 4

4.1

4.2

Exception Handling

.................................................................................. 69

4.3

4.4

Overview ........................................................................................................................

Reset

........................................................................................................................

4.2.1

Overview.........................................................................................................

4.2.2

Reset Sequence ...............................................................................................

4.2.3

Disabling of Interrupts after Reset..................................................................

Interrupts ........................................................................................................................

4.3.1

Overview.........................................................................................................

4.3.2

Interrupt-Related Registers.............................................................................

4.3.3

External Interrupts ..........................................................................................

4.3.4

Internal Interrupts ...........................................................................................

4.3.5

Interrupt Handling ..........................................................................................

4.3.6

Interrupt Response Time.................................................................................

4.3.7

Precaution .......................................................................................................

Note on Stack Handling..................................................................................................

Section 5

5.1

Wait-State Controller

............................................................................... 87

5.2

5.3

Overview ........................................................................................................................

5.1.1

Features...........................................................................................................

5.1.2

Block Diagram................................................................................................

5.1.3

Input/Output Pins............................................................................................

5.1.4

Register Description .......................................................................................................

5.2.1

Wait-State Control Register (WSCR).............................................................

Wait Modes.....................................................................................................................

Section 6

6.1

Clock Pulse Generator

............................................................................. 93

6.2

6.3

6.4

Overview ........................................................................................................................ 93

6.1.1

Block Diagram................................................................................................ 93

6.1.2

Wait-State Control Register (WSCR)............................................................. 94

Oscillator Circuit ............................................................................................................ 95

Duty Adjustment Circuit................................................................................................. 100

Prescaler ........................................................................................................................ 100

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