FX-730
Low Jitter VCSO Frequency Translator
Features
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5 x 7.5 x 2.5 mm Package
Frequency Translation up to 850 MHz
VCSO based PLL for Ultra-Low Jitter
CMOS / LVDS / LVPECL Inputs compatible
Differential LVPECL or LVDS Output
CMOS Lock Detect
External Divider for Input Frequencies < 19 MHz
0°/70°C or -40°/+85°C Temperature Range
Fully Compatible for Lead Free Assembly
Description
The FX-730 is a low jitter precision frequency translator
used to translate input frequencies such as 19.44,
38.88, 77.76 MHz, etc. to a binary multiple frequency as
high as 850 MHz. The FX-730’s superior jitter
performance is achieved through the PLL’s integrated
VCSO. The FX-730 is housed in a hermetically sealed
leadless surface mount package offered on tape and
reel.
Applications
Description
Standard
INCITS 352-2002
INCITS 364-2003
IEEE 802.3ae
ITU-T G.709
GR-253-CORE Issue 3
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1-2-4 Gigabit FC
10 Gigabit FC
10GbE LAN / WAN
OC-192
SONET / SDH
FEC (Forward Error Correction) Scaling
Figure 1. Functional Block Diagram
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 1 of 8
Tel: 1-88-VECTRON-1
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Web:
www.vectron.com
Rev: 24Jul07
FX-730 Low Jitter VCSO Frequency Translator
Table 1. Electrical Performance
Parameter
Frequency
Input Frequency
Output Frequency
Capture Range
(ordering option)
F
IN
F
OUT
19.44
125
±32, ±50, or ±100
2.97
3.3
3.63
100
V
CC
0.8
3.00
850
850
MHz
MHz
ppm
V
mA
V
V
V
V
V
V
mV-pp
V
mV-pp
mA
ps
ps
%
ps-rms
ps-rms
°C
2,3
2,3
2,3
2,3
5
4,5
4,5
2,3
5
5
1,3
1,2,3
1,2,3
1,2,3
2,3
3
2,3
Symbol
Minimum
Typical
Maximum
Units
Notes
APR
V
CC
I
CC
V
IH
V
IL
Supply
Voltage
Current (No Load)
LVCMOS Input
Input High Voltage
Input Low Voltage
2
0
0.20
V
OH
V
OL
0.9*V
CC
0.1*V
CC
V
CC
-1.4
450
V
CC
-2.0
250
I
OUT
t
R
t
F
SYM
Φ
J
Φ
J
T
OP
V
CC
-1.25
600
V
CC
-1.6
410
V
CC
-1.0
950
V
CC
-1.3
450
20
400
400
55
0.5
0.4
LVPECL Input
Peak-Peak Amplitude Swing
6,7
Lock Detect Output
Output High Voltage
Logic Low Voltage
Outputs
Mid Level - LVPECL
Swing - LVPECL
Mid Level - LVDS
Swing - LVDS
Current
Rise Time
Fall Time
Symmetry
Jitter Generation - 622.08 MHz output
(12 kHz – 20 MHz BW)
(50 kHz – 80 MHz BW)
45
50
0.21
0.12
0/70, -40/85
Operating Temp.
(ordering option)
1. See Standard Frequencies and Ordering Information.
2. Parameters are tested with production test circuit below (Fig 1).
3. Parameters are tested at ambient temperature with test limits guard banded for specified operating temperature.
4. Measured from 20% to 80% of a full output swing (Fig 2).
5. Not tested in production, guaranteed by design, verified at qualification.
6. Minimum Input Low Voltage not to exceed 2.125 V. Minimum Input High Voltage not to go below 1.49 V.
7. AC coupling is recommended. There is an internal pull-up and pull-down resistor on all clock inputs (Fin, BRCLK).
Figure 1. LVPECL Test Circuit
Figure 2. 10K LVPECL Waveform
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 2 of 8
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 24Jul07
FX-730 Low Jitter VCSO Frequency Translator
Outline Diagram
Suggested Pad Layout
1.02
[0.040]
1.96
[0.077]
0.25
[0.010]
1.27
[0.050]
0.64
[0.025]
4.14
[0.163]
1.02
[0.040]
0.20
[0.008]
1.45
[0.057]
2.54
[0.100]
5.08
[0.200]
2.07
1.27
[0.081]
[0.050]
3.28
[0.129]
mm
[inch]
Figure 3.
Figure 4.
Table 2. Pin Out
Pad #
1
Symbol
BRCLK
I/O
I
Level
NC or
LVPECL, LVDS
CMOS
Supply
CMOS
Supply
Analog
Analog
LVPECL or
LVDS
LVPECL or
LVDS
Supply
LVPECL
Function
NC or
For external divider applications = PD Feedback Frequency
Lock Detect
Logic “0” = FX Locked
Logic “1” = No input
Output transitioning = Out of Lock
Case and Electrical Ground
FX Operating Mode
Logic “0” = Standard PLL Operation
Normal setting
Logic “1” = FIN coupled to FOUT
Case and Electrical Ground
Loop Filter Node
Complementary Loop Filter Node
Frequency Output
Complementary Frequency Output
Power Supply Voltage (+3.3V ±5%)
Complementary Input Frequency
For CMOS inputs, AC-couple unused input to ground or negative supply.
2
3
4
5
6
7
8
9
10
11
12
LD
1
O
GND
2
GND
MODE
GND
LFN
CLFN
FOUT
CFOUT
VCC
CFIN
FIN
I
GND
O
O
I
I
I
1.
2.
3.
4.
CMOS or
Input Frequency
LVPECL
GND
GND
Supply
13
Case and Electrical Ground
NC or
NC or
CBRCLK
I
14
LVPECL, LVDS
For external divider applications = Comp. PD Feedback Frequency
It is recommended that a buffer driver is used for best noise isolation.
Do not leave the MODE pin floating, it should be set to logic 0 or ground for normal operation.
BRCLK and CBRCLK should be left floating if not used.
FIN, CFIN, BRCLK, and CBRCLK have internal pull-up/pull-down resistors and it is recommended to AC couple these inputs.
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 3 of 8
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 24Jul07
FX-730 Low Jitter VCSO Frequency Translator
Tape and Reel (EIA-481-2-A)
Po
ØDo
W2
F
W
D
C
N
A
P1
W1
B
Tape Dimensions (mm)
Dimension
Tolerance
FX-730
Reel Dimensions (mm)
Do
Typ
1.5
W
Typ
16
F
Typ
7.5
Po
Typ
4
P1
Typ
8
A
Typ
178
B
Min
1.5
C
Typ
13
D
Min
20.2
N
Min
50
W1
Typ
16.4
W2
Max
22.4
# Per
Reel
200
Table 3. Absolute Maximum Ratings
Parameter
Power Supply
Input Current
Output Current
Storage Temperature
Soldering Temperature/Duration
Symbol
V
CC
I
IN
I
OUT
T
STR
T
PEAK
/ t
P
Ratings
0 to 6
100
25
-55 to 125
260 / 40
Unit
V
mA
mA
°C
°C/sec
Stresses in excess of the absolute maximum ratings can permanently damage the device. Also, exposure to
these absolute maximum ratings for extended periods can adversely affect device reliability. Functional operation
is not implied at these or any other conditions in excess of those represented in the operational sections of this
data sheet. Permanent damage is also possible if any device input draws greater than 100 mA.
Application Circuits
Please contact Vectron application engineering for assistance.
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 4 of 8
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 24Jul07
FX-730 Low Jitter VCSO Frequency Translator
Reliability
VI qualification includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR
reflow simulation. The FX-730 family is undergoing the following qualification tests:
Table 4. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Moisture Sensitivity Level Rating
eliability
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2016
MSL 1
Handling Precautions
Although ESD protection circuitry has been designed into the FX-730 proper precautions should be taken when
handling and mounting. VI employs a human body model (HBM), a charged-device model (CDM), and machine
model (MM) for ESD susceptibility testing and design protection evaluation.
Table 5. ESD Ratings – LVPECL Output
Model
Human Body Model
Charged Device Model
Machine Model
Class
1A
C5
M1
Minimum
350 V
1000 V
50 V
Conditions
MIL-STD 883, Method 3015
JEDEC, JESD22-C101
ESD STM5.2-1999
Table 6. Reflow Profile (IPC/JEDEC J-STD-020C)
Parameter
PreHeat Time
Ramp Up
Time Above 217
o
C
Time To Peak Temperature
Time At 260
o
C
Ramp Down
Symbol
t
S
R
UP
t
L
t
AMB-P
t
P
R
DN
Value
60 sec Min, 180 sec Max
o
3 C/sec Max
60 sec Min, 150 sec Max
480 sec Max
20 sec Min, 40 sec Max
o
6 C/sec Max
Temperature (DegC)
The device has been qualified to meet the JEDEC
standard for Pb-Free assembly. The temperatures
and time intervals listed are based on the Pb-Free
small body requirements. The temperatures refer to
the topside of the package, measured on the
package body surface. The FX-730 device is
hermetically sealed so an aqueous wash is not an
issue.
260
t
L
R
t
P
R
DN
t
S
t
AMB-P
217
200
150
25
Time (sec)
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 5 of 8
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 24Jul07
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