ispLSI2128E-180LT176 datasheet, PDF

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ispLSI2128E-180LT176: DescriptionEE PLD, 7.5 ns, PQFP176; CategoryProgrammable logic devices Programmable logic; File Size109KB，11 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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ispLSI2128E-180LT176 Overview

EE PLD, 7.5 ns, PQFP176

ispLSI2128E-180LT176 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	QFP
package instruction	TQFP-176
Contacts	176
Reach Compliance Code	not_compliant
ECCN code	EAR99
Other features	YES
maximum clock frequency	125 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G176
JESD-609 code	e0
JTAG BST	NO
length	24 mm
Humidity sensitivity level	3
Dedicated input times	4
Number of I/O lines	128
Number of macro cells	128
Number of terminals	176
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4 DEDICATED INPUTS, 128 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP176,1.0SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	225
power supply	3.3/5,5 V
Programmable logic type	EE PLD
propagation delay	7.5 ns
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	24 mm
Base Number Matches	1

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ispLSI 2128E

In-System Programmable

SuperFAST™ High Density PLD

Features

• SUPERFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 6000 PLD Gates

— 128 I/O Pins, Eight Dedicated Inputs

— 128 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional/JEDEC Upward Compatible with

ispLSI 2128 Devices

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

max

= 180 MHz Maximum Operating Frequency

—

= 5.0 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— 5V Programmable Logic Core

— ispJTAG™ In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port

— User-Selectable 3.3V or 5V I/O Supports Mixed-

Voltage Systems

— PCI Compatible Outputs

— Open-Drain Output Option

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Functional Block Diagram

Output Routing Pool (ORP)

GLB

Global Routing Pool (GRP)

Output Routing Pool (ORP)

CLK 0

CLK 1

CLK 2

0139(9A)/2128

Description

The ispLSI 2128E is a High Density Programmable Logic

Device. The device contains 128 Registers, 128 Univer-

sal I/O pins, eight Dedicated Input pins, three Dedicated

Clock Input pins, two dedicated Global OE input pins and

a Global Routing Pool (GRP). The GRP provides com-

plete interconnectivity between all of these elements.

The ispLSI 2128E features 5V in-system programmabil-

ity and in-system diagnostic capabilities. The ispLSI

2128E offers non-volatile reprogrammability of all logic,

as well as the interconnect to provide truly reconfigurable

systems.

The basic unit of logic on the ispLSI 2128E device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. D7 (see Figure 1). There are a total of 32 GLBs in the

ispLSI 2128E device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or

registered.Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any GLB on the device.

The device also has 128 I/O cells, each of which is

directly connected to an I/O pin. Each I/O cell can be

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

November 1998

2128e_02

Output Routing Pool (ORP)

Logic

Array

Output Routing Pool (ORP)

ispLSI2128E-180LT176 Related Products

	ispLSI2128E-180LT176	2128E	ispLSI2128E-100LT176	ispLSI2128E-135LT176
Description	EE PLD, 7.5 ns, PQFP176	EE PLD, 7.5 ns, PQFP176	EE PLD, 7.5 ns, PQFP176	EE PLD, 7.5 ns, PQFP176
Number of terminals	176	176	176	176
Maximum operating temperature	70 °C	70 Cel	70 °C	70 °C
organize	4 DEDICATED INPUTS, 128 I/O	4 DEDICATED INPUTS, 128 I/O	4 DEDICATED INPUTS, 128 I/O	4 DEDICATED INPUTS, 128 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD
surface mount	YES	Yes	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal location	QUAD	QUAD	QUAD	QUAD
Is it lead-free?	Contains lead	-	Contains lead	Contains lead
Is it Rohs certified?	incompatible	-	incompatible	incompatible
Maker	Lattice	-	Lattice	Lattice
Parts packaging code	QFP	-	QFP	QFP
package instruction	TQFP-176	-	TQFP-176	TQFP-176
Contacts	176	-	176	176
Reach Compliance Code	not_compliant	-	not_compliant	not_compliant
ECCN code	EAR99	-	EAR99	EAR99
Other features	YES	-	IN-SYSTEM PROGRAMMABLE	IN-SYSTEM PROGRAMMABLE
maximum clock frequency	125 MHz	-	77 MHz	100 MHz
In-system programmable	YES	-	YES	YES
JESD-30 code	S-PQFP-G176	-	S-PQFP-G176	S-PQFP-G176
JESD-609 code	e0	-	e0	e0
JTAG BST	NO	-	NO	NO
length	24 mm	-	24 mm	24 mm
Humidity sensitivity level	3	-	3	3
Dedicated input times	4	-	4	4
Number of I/O lines	128	-	128	128
Number of macro cells	128	-	128	128
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	-	LFQFP	LFQFP
Encapsulate equivalent code	QFP176,1.0SQ,20	-	QFP176,1.0SQ,20	QFP176,1.0SQ,20
Package shape	SQUARE	-	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	-	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	225	-	225	256
power supply	3.3/5,5 V	-	3.3/5,5 V	3.3/5,5 V
propagation delay	7.5 ns	-	13 ns	10 ns
Certification status	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	-	1.6 mm	1.6 mm
Maximum supply voltage	5.25 V	-	5.25 V	5.25 V
Minimum supply voltage	4.75 V	-	4.75 V	4.75 V
Nominal supply voltage	5 V	-	5 V	5 V
technology	CMOS	-	CMOS	CMOS
Terminal surface	Tin/Lead (Sn85Pb15)	-	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal pitch	0.5 mm	-	0.5 mm	0.5 mm
Maximum time at peak reflow temperature	30	-	30	30
width	24 mm	-	24 mm	24 mm
Base Number Matches	1	-	1	1

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