FST16209 18-Bit Bus Exchange Switch
September 1997
Revised December 1999
FST16209
18-Bit Bus Exchange Switch
General Description
The Fairchild Switch FST16209 provides 18-bits of high-
speed CMOS TTL-compatible bus switching or exchang-
ing. The low on resistance of the switch allows inputs to be
connected to outputs without adding propagation delay or
generating additional ground bounce noise.
The device operates as a 18-bit bus switch or a 9-bit bus
exchanger, which allows data exchange between the four
signal ports via the data-select terminals.
Features
s
4Ω switch connection between two ports.
s
Minimal propagation delay through the switch.
s
Low l
CC
.
s
Zero bounce in flow-through mode.
s
Control inputs compatible with TTL level.
Ordering Code:
Order Number
FST16209MEA
FST16209MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
Truth Table
S2
L
L
L
L
H
H
H
H
S1
L
L
H
H
L
L
H
H
S0
L
H
L
H
L
H
L
H
A
1
Z
B
1
B
2
Z
Z
Z
B
1
B
2
A
2
Z
Z
Z
B
1
B
2
Z
B
2
B
1
Function
Disconnect
A
1
=
B
1
A
1
=
B
2
A
2
=
B
1
A
2
=
B
2
Disconnect
A
1
=
B
1
, A
2
=
B
2
A
1
=
B
2
, A
2
=
B
1
Pin Descriptions
Pin Name
S2, S1, S0
A
1
, A
2
B
1
, B
2
Description
Data-select inputs
Bus A
Bus B
© 1999 Fairchild Semiconductor Corporation
DS500056
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FST16209
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Switch Voltage (V
S
)
DC Input Voltage (V
IN
)(Note 2)
DC Input Diode Current (l
IK
) V
IN
<0V
DC Output (I
OUT
) Sink Current
DC V
CC
/GND Current (I
CC
/I
GND
)
Storage Temperature Range (T
STG
)
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−50mA
128mA
+/−
100mA
−65°C
to
+150 °C
Recommended Operating
Conditions
(Note 3)
Power Supply Operating (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Input Rise and Fall Time (t
r
, t
f
)
Switch Control Input
Switch I/O
Free Air Operating Temperature (T
A
)
0nS/V to 5nS/V
0nS/V to DC
−40 °C
to
+85 °C
4.0V to 5.5V
0V to 5.5V
0V to 5.5V
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3:
Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
I
I
I
OFF
R
ON
Parameter
Clamp Diode Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
OFF-STATE Leakage Current
Switch On Resistance
(Note 5)
V
CC
(V)
4.5
4.0–5.5
4.0–5.5
5.5
0
5.5
4.5
4.5
4.5
4.0
I
CC
∆
I
CC
Quiescent Supply Current
Increase in I
CC
per Input
5.5
5.5
4
4
8
14
2.0
0.8
±1.0
10
±1.0
7
7
12
20
3
2.5
T
A
= −40 °C
to
+85 °C
Min
Typ
(Note 4)
Units
Max
−1.2
V
V
V
µA
µA
µA
Ω
Ω
Ω
Ω
µA
mA
0
≤
V
IN
≤
5.5V
V
IN
=
5.5V
0
≤
A, B
≤
V
CC
V
IN
=
0V, I
IN
=
64mA
V
IN
=
0V, I
IN
=
30mA
V
IN
=
2.4V, I
IN
=
15mA
V
IN
=
2.4V, I
IN
=
15mA
V
IN
=
V
CC
or GND, I
OUT
=
0
One input at 3.4V
Other inputs at V
CC
or GND
Note 4:
Typical values are at V
CC
=
5.0V and T
A
= +25°C
Note 5:
Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Conditions
I
IN
= −18mA
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2
FST16209
AC Electrical Characteristics
T
A
= −40 °C
to
+85 °C,
Symbol
Parameter
C
L
=
50pF, R
U
=
R
D
=
500Ω
V
CC
=
4.5
−
5.5V
Min
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZH
, t
PZL
t
PHZ
, t
PLZ
Prop Delay Bus to Bus (Note 6)
Prop Delay S to Bus
Output Enable Time, S to A or B
Output Disable Time S to A or B
1.5
1.5
1.0
Max
0.25
7.0
7.5
8.5
V
CC
=
4.0V
Min
Max
0.25
7.0
8.0
9.0
ns
ns
ns
ns
V
I
=
OPEN
V
I
=
OPEN
V
I
=
7V for t
PZL
V
I
=
OPEN for t
PZH
V
I
=
7V for t
PLZ
V
I
=
OPEN for t
PHZ
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Units
Conditions
Figure No.
Note 6:
This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
(Note 7)
Symbol
C
IN
C
I/O
Parameter
Control pin Input Capacitance
Input/Output Capacitance
Typ
3
10
Max
Units
pF
pF
Conditions
V
CC
=
5.0V
V
CC
=
5.0V,
S0, S1, and S2
=
GND
Note 7:
T
A
= +25°C,
f
=
1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50
Ω
source terminated in 50
Ω
Note: C
L
includes load and stray capacitance
Note: Input PRR
=
1.0 MHz, t
W
=
500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3
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FST16209
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS48A
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4
FST16209 18-Bit Bus Exchange Switch
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
5
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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