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544BAAC001808BBGR

Description
LVDS Output Clock Oscillator,
CategoryPassive components    oscillator   
File Size1MB,33 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
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544BAAC001808BBGR Overview

LVDS Output Clock Oscillator,

544BAAC001808BBGR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Reach Compliance Codeunknown
JESD-609 codee4
Oscillator typeLVDS
Terminal surfaceGold (Au) - with Nickel (Ni) barrier
Base Number Matches1
Ultra Series
Crystal Oscillator
Si544 Data Sheet
Ultra Low Jitter I2C Programmable XO (150 fs), 0.2 to 1500 MHz
The Si544 Ultra Series
oscillator utilizes Silicon Laboratories’ advanced 4
th
generation DSPLL
®
technology to provide an ultra-low jitter, low phase noise
clock at any output frequency. The device is user-programmed via simple
I2C commands to provide any frequency from 0.2 to 1500 MHz with <1 ppb
resolution and maintains exceptionally low jitter for both integer and fraction-
al frequencies across its operating range. The Si544 offers excellent reliabili-
ty and frequency stability as well as guaranteed aging performance. On-chip
power supply filtering provides industry-leading power supply noise rejection,
simplifying the task of generating low jitter clocks in noisy systems that use
switched-mode power supplies. The Si544 has a dramatically simplified sup-
ply chain that enables Silicon Labs to ship custom frequency samples 1-2
weeks after receipt of order. Unlike a traditional XO, where a different crystal
is required for each output frequency, the Si544 uses one simple crystal and
a DSPLL IC-based approach to provide the desired output frequency. The
Si544 is factory-configurable for a wide variety of user specifications, includ-
ing startup frequency, I2C address, output format, and OE pin location/
polarity. Specific configurations are factory-programmed at time of shipment,
eliminating the long lead times associated with custom oscillators.
Pin Assignments
SDA
OE/FS/NC
1
7
6
VDD
KEY FEATURES
• I2C programmable to any frequency from 0.2 to
1500 MHz with < 1 ppb resolution
• Very low jitter: 150 fs Typ RMS (12 kHz – 20 MHz)
• Configure up to 4 pin-selectable startup frequencies
• I2C interface supports 100 kbps, 400 kbps, and 1
Mbps (Fast Mode Plus)
• Excellent PSRR and supply noise immunity: –80
dBc Typ
• 3.3 V, 2.5 V and 1.8 V V
DD
supply operation from
the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and Dual
CMOS output options
• 3.2x5, 5x7 mm package footprints
• Samples available with 1-2 week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics, PAM4
• 10G/40G/100G optical ethernet
• 3G-SDI/12G-SDI/24G-SDI broadcast video
• Servers, switches, storage, search acceleration
• Test and measurement
• FPGA/ASIC clocking
NC/OE/FS
GND
2
3
8
SCL
(Top View)
5
4
CLK–
CLK+
Pin #
1, 2
3
4
5
6
7
8
Descriptions
Selectable via ordering option
OE = Output enable; FS = Frequency Select; NC = No connect
GND = Ground
CLK+ = Clock output
CLK- = Complementary clock output. Not used for CMOS.
VDD = Power supply
SDA = I2C Serial Data
SCL = I2C Serial Clock
NVM
Control
OSC
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
DCO
Low
Noise
Driver
Digital
Phase
Detector
Phase Error
Cancellation
Phase Error
Fractional
Divider
Digital
Loop
Filter
Flexible
Formats,
1.8V – 3.3V
Operation
Power Supply Regulation
OE, Frequency Select
(I2C and Pin Control)
Built-in Power Supply
Noise Rejection
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