80960JS/JC 3.3 V Microprocessor
Advance Information Datasheet
Product Features
s
s
s
s
s
Pin/Code Compatible with all 80960Jx
Processors
High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Core Clock Rate is:
80960JS 1x the Bus Clock
80960JC 2x the Bus Clock
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
Two-Way Set Associative Instruction
Cache
— 16 Kbyte
— Programmable Cache-Locking
Mechanism
Direct Mapped Data Cache
— 4 Kbyte
— Write Through Operation
On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority
Interrupts
s
s
s
s
s
s
s
s
On-Chip Data RAM
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
3.3 V Supply Voltage
— 5 V Tolerant Inputs
— TTL Compatible Outputs
High Bandwidth Burst Bus
— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
High-Speed Interrupt Controller
— 31 Programmable Priorities
— Eight Maskable Pins plus NMI#
— Up to 240 Vectors in Expanded Mode
Two On-Chip Timers
— Independent 32-Bit Counting
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
Halt Mode for Low Power
IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
Packages
— 132-Lead Pin Grid Array (PGA)
— 132-Lead Plastic Quad Flat Pack
(PQFP)
— 196-Ball Mini Plastic Ball Grid Array
(MPBGA)
Notice:
This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 273200-002
December, 1998
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 80960JS and 80960JC microprocessors may contain design defects or errors known as errata which may cause the products to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
Advance Information Datasheet
80960JS/JC 3.3 V Microprocessor
Contents
1.0
2.0
Introduction
.................................................................................................................. 7
80960Jx Overview
...................................................................................................... 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
80960 Processor Core .......................................................................................... 9
Burst Bus............................................................................................................. 10
Timer Unit............................................................................................................ 10
Priority Interrupt Controller .................................................................................. 10
Instruction Set Summary .....................................................................................11
Faults and Debugging ......................................................................................... 11
Low Power Operation ..........................................................................................11
Test Features ...................................................................................................... 12
Memory-Mapped Control Registers .................................................................... 12
Data Types and Memory Addressing Modes ...................................................... 12
3.0
Package Information: 80960JS/JC 3.3 V Processors
................................ 14
3.1
Pin Descriptions .................................................................................................. 15
3.1.1 Functional Pin Definitions .......................................................................15
3.1.2 80960Jx 132-Lead PGA Pinout.............................................................. 21
3.1.3 80960Jx 132-Lead PQFP Pinout............................................................ 25
3.1.4 80960Jx 196-Ball MPBGA Pinout .......................................................... 28
Package Thermal Specifications .........................................................................33
Thermal Management Accessories..................................................................... 36
3.3.1 Heatsinks................................................................................................ 36
3.2
3.3
4.0
Electrical Specifications 80960JS/JC 3.3 V Processor
............................. 37
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Absolute Maximum Ratings................................................................................. 37
Operating Conditions........................................................................................... 37
Connection Recommendations ........................................................................... 38
VCC5 Pin Requirements (VDIFF) .......................................................................38
VCCPLL Pin Requirements................................................................................. 39
DC Specifications ................................................................................................ 40
AC Specifications ................................................................................................ 42
4.7.1 AC Test Conditions and Derating Curves .............................................. 44
4.7.2 AC Timing Waveforms ........................................................................... 49
5.0
Bus Functional Waveforms
.................................................................................. 55
5.1
5.2
Basic Bus States .................................................................................................65
Boundary-Scan Register .....................................................................................66
6.0
7.0
Device Identification 80960JS/JC 3.3 V Processor
..................................... 72
Revision History
....................................................................................................... 74
Advance Information Datasheet
3
80960JS/JC 3.3 V Microprocessor
Figures
1
2
3
4
5
6
7
8
9
10
11
12
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14
15
16
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22
23
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26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
80960Jx Microprocessor Package Options........................................................... 7
80960JS/JC Block Diagram .................................................................................. 9
132-Lead Pin Grid Array Top View - Pins Facing Down ..................................... 21
132-Lead Pin Grid Array Bottom View - Pins Facing Up..................................... 22
132-Lead PQFP - Top View ................................................................................ 25
196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down .................. 28
196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up .................. 29
VCC5 Current-Limiting Resistor .......................................................................... 38
VCCPLL Lowpass Filter ...................................................................................... 39
AC Test Load ...................................................................................................... 44
Output Delay or Hold vs. Load Capacitance (3.3 V Signals) .............................. 45
Output Delay or Hold vs. Load Capacitance (5 V Signals) ................................. 45
T
LX
vs. AD Bus Load Capacitance (3.3 V Signals) ............................................. 46
T
LX
vs. AD Bus Load Capacitance (5 V Signals) ................................................ 46
80960JC I
CC
Active (Power Supply) vs. Frequency............................................ 47
80960JC I
CC
Active (Thermal) vs. Frequency..................................................... 47
80960JS I
CC
Active (Power Supply) vs. Frequency ............................................ 48
80960JS I
CC
Active (Thermal) vs. Frequency ..................................................... 48
CLKIN Waveform ................................................................................................ 49
T
OV1
Output Delay Waveform ............................................................................. 49
T
OF
Output Float Waveform................................................................................ 50
T
IS1
and T
IH1
Input Setup and Hold Waveform ................................................... 50
T
IS2
and T
IH2
Input Setup and Hold Waveform ................................................... 50
T
IS3
and T
IH3
Input Setup and Hold Waveform ................................................... 51
T
IS4
and T
IH4
Input Setup and Hold Waveform ................................................... 51
T
LX
, T
LXL
and T
LXA
Relative Timings Waveform................................................. 52
DT/R# and DEN# Timings Waveform ................................................................. 52
TCK Waveform.................................................................................................... 53
T
BSIS1
and T
BSIH1
Input Setup and Hold Waveforms ......................................... 53
T
BSOV1
and T
BSOF1
Output Delay and Output Float Waveform.......................... 53
T
BSOV2
and T
BSOF2
Output Delay and Output Float Waveform.......................... 54
T
BSIS2
and T
BSIH2
Input Setup and Hold Waveform ........................................... 54
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus ......... 55
Burst Read and Write Transactions Without Wait States, 32-Bit Bus ................. 56
Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus........................... 57
Burst Read and Write Transactions Without Wait States, 8-Bit Bus ................... 58
Burst Read and Write Transactions With 1, 0 Wait States and
Extra Tr State on Read, 16-Bit Bus ..................................................................... 59
Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit Bus, Little Endian ................................................. 60
HOLD/HOLDA Waveform For Bus Arbitration .................................................... 61
Cold Reset Waveform ......................................................................................... 62
Warm Reset Waveform ....................................................................................... 63
Entering the ONCE State .................................................................................... 64
Bus States with Arbitration .................................................................................. 66
Summary of Aligned and Unaligned Accesses (32-Bit Bus) ............................... 70
Summary of Aligned and Unaligned Accesses (32-Bit Bus) ............................... 71
80960JS/JC Device Identification Register ......................................................... 72
4
Advance Information Datasheet
80960JS/JC 3.3 V Microprocessor
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
80960Jx Instruction Set....................................................................................... 13
Pin Description Nomenclature............................................................................. 15
Pin Description — External Bus Signals ............................................................. 16
Pin Description — Processor Control Signals, Test Signals and Power ............. 19
Pin Description — Interrupt Unit Signals ............................................................. 20
132-Lead PGA Pinout — In Signal Order............................................................ 23
132-Lead PGA Pinout — In Pin Order ................................................................ 24
132-Lead PQFP Pinout — In Signal Order ......................................................... 26
132-Lead PQFP Pinout — In Pin Order .............................................................. 27
196-Ball MPBGA Pinout — In Signal Order ........................................................ 30
196-Ball MPBGA Pinout — In Pin Order ............................................................. 31
132-Lead PGA Package Thermal Characteristics...............................................34
196-Ball MPBGA Package Thermal Characteristics ........................................... 34
132-Lead PQFP Package Thermal Characteristics ............................................ 35
Maximum T
A
at Various Airflows in °C (80960JC) .............................................. 35
Maximum T
A
at Various Airflows in °C (80960JS)...............................................36
Absolute Maximum Ratings................................................................................. 37
80960JS/JC Operating Conditions ...................................................................... 37
VDIFF Parameters .............................................................................................. 39
80960JS/JC DC Characteristics.......................................................................... 40
80960JS/JC I
CC
Characteristics .......................................................................... 40
80960JS/JC AC Characteristics .......................................................................... 42
Note Definitions for Table 22, “80960JC/JS AC Characteristics” ........................ 44
Boundary-Scan Register Bit Order...................................................................... 67
Natural Boundaries for Load and Store Accesses .............................................. 68
Summary of Byte Load and Store Accesses....................................................... 68
Summary of Short Word Load and Store Accesses............................................ 68
Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)........................... 69
80960JS/JC Device Type and Stepping Reference ............................................ 72
Fields of 80960JS/JC Device ID.......................................................................... 73
80960JS/JC Device ID Model Types................................................................... 73
Datasheet Revision History ................................................................................. 74
Advance Information Datasheet
5
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