notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00E
09/08/2010
1
IS43DR32800A, IS43/46DR32801A
GENERAL DESCRIPTION
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue
for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the active
command are used to select the bank and row to be accessed (BA0-BA1 select the bank; A0-A11/A12 select the
row and A0-A7/A8 select the column). The address bits registered coincident with the Read or Write command are
used to select the starting column location for the burst access and to determine if the auto precharge command is
to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed
information covering device initialization, register definition, command descriptions and device operation.
FUNCTIONAL BLOCK DIAGRAM
CK
CK
CKE
ODT
CS
RAS
CAS
WE
COMMAND
DECODER
&
CLOCK
GENERATOR
REFRESH
CONTROLLER
DQ0 – DQ31
DLL
SELF
REFRESH
CONTROLLER
MODE
REGISTERS
MULTIPLEXER
ODT CIRCUIT
ROW DECODER
REFRESH
COUNTER
ROW DECODER
MEMORY CELL
ARRAY
MEMORY CELL
ARRAY
BANK 0
BANK 0
SENSE AMP
SENSE AMP
OUTPUT
DATA
BUFFER
INPUT
DATA
BUFFER
A0 – An,
BA0 – BA1
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
DM0 – DM3
BANK CONTROL LOGIC
I/O GATE
&
MASK LOGIC
DATA
STROBE
GENERATOR
COLUMN
ADDRESS LATCH
COLUMN DECODER
COLUMN DECODER
COLUMN DECODER
COLUMN DECODER
BURST COUNTER
DQS0 – DQS3,
DQS0 – DQS3
COLUMN ADDRESS
BUFFER
Notes:
1.) An: n = no. of address pins – 1
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00E
09/08/2010
IS43DR32800A, IS43/46DR32801A
PIN DESCRIPTION TABLE
Symbol
CK, CK
Type
Input
Function
Clock: CK and CK are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and negative edge of CK.
Output (read) data is referenced to the crossings of CK and CK (both directions of
crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signals
and device input buffers and output drivers. Taking CKE LOW provides Precharge
Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row
Active in any bank). CKE is synchronous for power down entry and exit, and for self
refresh entry. CKE is asynchronous for self refresh exit. After VREF has become
stable during the power on and initialization sequence, it must be maintained for
proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF
must be maintained to this input. CKE must be maintained HIGH throughout read and
write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during
power-down. Input buffers, excluding CKE, are disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for
external Rank selection on systems with multiple Ranks. CS is considered part of the
command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal
to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS, DQM
signals. The ODT pin will be ignored if the EMR(1) is programmed to disable ODT.
Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH coincident with that input data during a Write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. The function of DM is enabled by EMRS command
to EMR(1).
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. Bank address also determines if the mode
register or one of the extended mode registers is to be accessed during a MRS or
EMRS command cycle.
Address Inputs: Provide the row address for Active commands and the column
address and Auto Precharge bit for Read/Write commands to select one location
out of the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0 -
BA1. The address inputs also provide the op-code during MRS or EMRS commands.
Standard Page option only: A12 is not used for addressing, but is necessary as an
input for the setting of the Mode Register (MRS) and Extended Mode Registers
(EMR). If not implemented for MRS/EMR, A12 can be left connected to Vss. It must
not be left floating.
CKE
Input
CS
Input
ODT
RAS, CAS, WE
Input
Input
(DM0-DM3)
Input
BA0 - BA1
Input
A0 - A12
Input
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00E
09/08/2010
3
IS43DR32800A, IS43/46DR32801A
Symbol
DQ0-31
Type
Input/
Output
Function
Data Input/Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. The data strobes DQS(n) may be used in single ended mode
or paired with optional complementary signals DQS(n) to provide differential pair
signaling to the system during both reads and writes. A control bit at EMR(1)[A10]
enables or disables all complementary data strobe signals.
Input/
Output
DQS0 corresponds to the data on DQ0-DQ7
DQS1 corresponds to the data on DQ8-DQ15
DQS2 corresponds to the data on DQ16-DQ23
DQS3 corresponds to the data on DQ24-DQ31
NC
VDDQ
VSSQ
VDDL
VSSDL
VDD
VSS
VREF
Supply
Supply
Supply
Supply
Supply
Supply
Supply
No Connect: No internal electrical connection is present.
DQ Power Supply: 1.8 V +/- 0.1 V
DQ Ground
DLL Power Supply: 1.8 V +/- 0.1 V
DLL Ground
Power Supply: 1.8 V +/- 0.1 V
Ground
Reference voltage
DQS, (DQS)
(DQS 0-3,
DQS 0-3)
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00E
09/08/2010
IS43DR32800A, IS43/46DR32801A
PIN CONFIGURATION
PACKAGE CODE: B
126-ball BGA for x32 (Top View) (11mm x 14mm Body, 0.8mm Ball Pitch)
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