K4D64163HF
64M DDR SDRAM
64Mbit DDR SDRAM
1M x 16Bit x 4 Banks
Double Data Rate Synchronous DRAM
Revision 1.1
August 2002
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev. 1.1(Aug. 2002)
K4D64163HF
Revision History
Revision 1.1 (August 6, 2002)
• Typo corrected
64M DDR SDRAM
Revision 1.0 (June 17, 2002)
• Defined DC spec
Revision 0.1 (May 20, 2002) -
Target Spec
• Typo corrected
Revision 0.0 (April 30, 2002) -
Target Spec
• Defined Target Specification
- 2 -
Rev. 1.1(Aug. 2002)
K4D64163HF
1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 3.3V + 5% power supply for device operation
• 2.5V + 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 2 DQS’s ( 1DQS / Byte )
64M DDR SDRAM
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 64ms refresh period (4K cycle)
• 66pin TSOP-II
• Maximum clock frequency up to 300MHz
• Maximum data rate up to 600Mbps/pin
ORDERING INFORMATION
Part NO.
K4D64163HF-TC33
K4D64163HF-TC36
K4D64163HF-TC40
K4D64163HF-TC50
K4D64163HF-TC60
Max Freq.
300MHz
275MHz
250MHz
200MHz
166MHz
Max Data Rate
600Mbps/pin
550Mbps/pin
500Mbps/pin
400Mbps/pin
333Mbps/pin
SSTL_2
66 pin TSOP-II
Interface
Package
GENERAL DESCRIPTION
FOR 1M x 16Bit x 4 Bank DDR SDRAM
The K4D64163H is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 16
bits, fabricated with SAMSUNG
’
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.2GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of
high performance memory system applications.
- 3 -
Rev. 1.1(Aug. 2002)
K4D64163HF
PIN CONFIGURATION
(Top View)
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CK
CK
CKE
NC
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
64M DDR SDRAM
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm Pin Pitch)
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
PIN DESCRIPTION
CK,CK
CKE
CS
RAS
CAS
WE
LDQS,UDQS
LDM,UDM
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
BA
0
, BA
1
A
0
~A
11
DQ
0
~ DQ
15
V
DD
V
SS
V
DDQ
V
SSQ
NC
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ
’
s
Ground for DQ
’
s
No Connection
- 4 -
Rev. 1.1(Aug. 2002)
K4D64163HF
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CK, CK*1
Input
Type
Function
64M DDR SDRAM
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
’
s and DM
’
s that are sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data Strobe : Output with read data, input with write data. Edge-
aligned with read data, centered in write data. Used to capture write
data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ;
UDQS corresponds to the data on DQ8-DQ15.
Input Data Mask : DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS. DM
pins include dummy loading internally, to matches the DQ and DQS
loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ;
UDM correspons to the data on DQ8-DQ15.
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
0
~ RA
11
, Column addresses : CA
0
~ CA
7
.
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
Reference voltage for inputs, used for SSTL interface.
This pin is recommended to be left "No connection" on the device
CKE
Input
CS
Input
RAS
CAS
WE
Input
Input
Input
LDQS,(U)DQS
Input/Output
LDM,UDM
Input
DQ
0
~ DQ
15
BA
0
, BA
1
A
0
~ A
11
V
DD
/V
SS
V
DDQ
/V
SSQ
V
REF
NC/RFU
Input/Output
Input
Input
Power Supply
Power Supply
Power Supply
No connection/
Reserved for future use
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
- 5 -
Rev. 1.1(Aug. 2002)
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