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CY24126SC

Description
Video Clock Generator, 120MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size106KB,5 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

CY24126SC Overview

Video Clock Generator, 120MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

CY24126SC Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerCypress Semiconductor
Parts packaging codeSOIC
package instruction0.150 INCH, SOIC-8
Contacts8
Reach Compliance Codecompliant
ECCN codeEAR99
JESD-30 codeR-PDSO-G8
JESD-609 codee0
length4.9 mm
Humidity sensitivity level1
Number of terminals8
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency120 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)220
power supply3.3 V
Master clock/crystal nominal frequency24 MHz
Certification statusNot Qualified
Maximum seat height1.72 mm
Maximum slew rate35 mA
Maximum supply voltage3.47 V
Minimum supply voltage3.14 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, VIDEO
Base Number Matches1
PRELIMINARY
CY24126
MediaClock™
for LCD Projectors
1CY2295
Features
• Integrated phase-locked loop
• Low jitter, high accuracy outputs
• 3.3V operation
• 8-pin SOIC package
Part Number
CY24126
Outputs
2
Input Frequency
24 MHz
Benefits
High-performance PLL tailored for projector applications
Meets critical timing requirements in complex system designs
Enables application compatibility
Industry standard package saves on board space
Output Frequencies
24 MHz, 48.00 MHz/120.00 MHz (selectable)
Logic Block Diagram
REF
XIN
XOUT
OSC
Q
Φ
VCO
P
OUTPUT
DIVIDERS
CLK
PLL
S0
S1
VDD
VSS
Pin Configurations
Table 1.
XIN (MHz)
CY24126
8-pin SOIC
XIN
VDD
S0
VSS
1
2
3
4
8
7
6
5
XOUT
S1
REF
CLK
S1
[1]
L
H
X
S0
L
L
H
CLK (MHz)
120.00
48.00
disable
Note
x5
x2
-
24.00
24.00
24.00
Note:
1. X = don’t care.
Cypress Semiconductor Corporation
Document #: 38-07326 Rev. *A
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised December 14, 2002
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