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MT58L128L32D1T-6

Description
Cache SRAM, 128KX32, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
Categorystorage    storage   
File Size445KB,26 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

MT58L128L32D1T-6 Overview

Cache SRAM, 128KX32, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100

MT58L128L32D1T-6 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCypress Semiconductor
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time3.5 ns
Other featuresPIPELINED ARCHITECTURE
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density4194304 bit
Memory IC TypeCACHE SRAM
memory width32
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count131072 words
character code128000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX32
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD (800)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
Base Number Matches1
4Mb: 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
4Mb SYNCBURST
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (V
DD
)
• Separate +3.3V isolated output buffer supply
(V
DD
Q)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
WRITE
• Three chip enables for simple depth expansion
and address pipelining
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down for portable applications
• 165-pin FBGA package
• 100-pin TQFP package
• Low capacitive bus loading
• x18, x32, and x36 versions available
MT58L256L18D1, MT58L128L32D1,
MT58L128L36D1
3.3V V
DD
, 3.3V I/O, Pipelined, Double-
Cycle Deselect
100-Pin TQFP
1
165-Pin FBGA
2
OPTIONS
• Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
256K x 18
128K x 32
128K x 36
• Packages
100-pin TQFP
165-pin FBGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
Part Number Example:
MARKING
-6
-7.5
-10
MT58L256L18D1
MT58L128L32D1
MT58L128L36D1
T
F*
None
IT
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
2. The 165-ball FBGA is not recommended for new
designs in the 4Mb density.
GENERAL DESCRIPTION
The Micron
®
SyncBurst
SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 4Mb SyncBurst SRAMs integrate a 256K x
18, 128K x 32, or 128K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock in-
put (CLK). The synchronous inputs include all ad-
dresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#) and global write
(GW#).
MT58L256L18D1T-6
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html. The 165-ball
FBGA is not recommended for new designs in the 4Mb density.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1_F.p65 – Rev. F, 1/03 EN
1
©2003, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
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