© 2003 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without
notice. Products may have minor variations to this publication, known as errata. PLX assumes no
liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX
products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc. Other
brands and names are property of their respective owners.
This device is not designed, intended, authorized, or warranted to be suitable for use in
medical, life-support applications, devices or systems or other critical applications.
PLX Part Number: PCI 6154-BB66BC; Former HiNT Part Number: HB2
Order Number: 6154-SIL-DB-P1-2.0
Printed in the USA, May 2003
PCI 6154 PCI-to-PCI Bridge
Adaptive High Performance Asynchronous 66 MHz 64-bit PCI-to-PCI Bridge for
Servers, Storage, Telecommunication, Networking- and Embedded Applications
PLX's latest PCI 6154 64-bit PCI-to-PCI bridge is designed for high performance, high availability applications in
bus expansions, programmable data transfer rate control, frequency conversions from slower PCI to faster PCI or
from faster PCI to slower PCI buses. PCI 6154 has sophisticated buffer management and buffer configuration
options designed to provide customizable performance optimization.
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PCI Local Bus Specification Rev 2.3
support
High speed PCI buffer supports 3.3V
signaling with 5V input signal tolerance
Asynchronous design supports standard
66MHz to 33MHz and faster secondary port
speed such as 33MHz to 40/50/60/66MHz
conversion
Programmable Address Translation to
Secondary Bus
Flow-Through 0 wait state burst up to 4K
bytes for optimal large volume data transfer
Supports up to 4 simultaneous posted write
transactions and 4 simultaneous Delayed
transactions in each direction
Provides 1K Bytes of buffering
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256 byte upstream posted write
buffer
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256 byte downstream posted write
buffer
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256 byte upstream read data buffer
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256 byte downstream read data
buffer
Programmable prefetch amount of up to 256
bytes for maximum read performance
optimization
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Supports out of order delayed transactions
Serial
EEPROM
loadable
and
programmable PCI READ ONLY Register
configurations.
External arbiter or programmable arbitration
for 9 bus masters on secondary interface
support
10 Secondary clock outputs with pin
controlled enable and individual maskable
control
PCI Mobile Design Guide and Power
Management D3 Cold Wakeup capable
4 GPIO pins with output control
Enhanced address decoding
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Support 32-bit I/O address range
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32-bit memory-mapped I/O address
range
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ISA aware mode for legacy support in
the first 64KB of I/O address range
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VGA addressing and palette snooping
support
Provides an IEEE standard 1149.1 JTAG
interface for boundary scan test
PCI 6154 uses Industry standard 31mm x
31mm 304 ball PBGA package
PCI 6154 Data Book v2.0
2003 PLX Technology, Inc. All rights reserved.
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