lS80C86 datasheet, PDF - EEWORLD Datasheet

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lS80C86: Description16-BIT, 5 MHz, MICROPROCESSOR, CDIP40; Categorysemiconductor The embedded processor and controller; File Size349KB，35 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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lS80C86 Overview

16-BIT, 5 MHz, MICROPROCESSOR, CDIP40

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80C86

March 1997

CMOS 16-Bit Microprocessor

Description

The Intersil 80C86 high performance 16-bit CMOS CPU is

manufactured using a self-aligned silicon gate CMOS pro-

cess (Scaled SAJI IV). Two modes of operation, minimum for

small systems and maximum for larger applications such as

multiprocessing, allow user conﬁguration to achieve the

highest performance level. Full TTL compatibility (with the

exception of CLOCK) and industry standard operation allow

use of existing NMOS 8086 hardware and software designs.

Features

• Compatible with NMOS 8086

• Completely Static CMOS Design

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C86)

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)

• Low Power Operation

- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500µA Max

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ

• 1MByte of Direct Memory Addressing Capability

• 24 Operand Addressing Modes

• Bit, Byte, Word and Block Move Operations

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

- Binary, or Decimal

- Multiply and Divide

• Wide Operating Temperature Range

- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0

C to +70

- l80C86 . . . . . . . . . . . . . . . . . . . . . . . . . -40

C to +85

- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55

C to +125

[ /Title

(80C86

)

/Sub-

ject

(CMO

S 16-

Bit

Micro-

proces-

sor)

/Autho

r ()

/Key-

words

(Inter-

sil

Corpo-

ration,

Inter-

sil

Corpo-

ration,

16 Bit

uP,

micro-

proces-

sor,

8086,

PC)

/Cre-

Ordering Information

PACKAGE

PDIP

TEMP. RANGE

C to +70

+70

+85

5MHz

CP80C86

8MHz

PKG.

NO.

CP80C86-2 E40.6

IP80C86-2

E40.6

-40

C to +85

C lP80C86

PLCC

CS80C86

-40

C to +85

C lS80C86

CERDIP

CD80C86

ID80C86

-40

CS80C86-2 N44.65

IS80C86-2

N44.65

CD80C86-2 F40.6

ID80C86-2

F40.6

-55

C to +125

C MD80C86/B MD80C86-

2/B

SMD#

CLCC

SMD#

-55

C to +125

C MR80C86/B MR80C86-

2/B

-55

C to +125

C 8405201QA 8405202QA F40.6

J44.A

-55

C to +125

C 8405201XA 8405202XA J44.A

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

File Number

2957.1

3-141

80C86

Pin Description

The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is

the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).

NUMBER

2-16, 39

SYMBOL

AD15-AD0

TYPE

I/O

DESCRIPTION

ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (T1) and

data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-

D0. It is LOW during Ti when a byte is to be transferred on the lower portion of the bus in memory

or I/O operations. Eight-bit oriented devices tied to the lower half would normally use A0 to con-

dition chip select functions (See BHE). These lines are active HIGH and are held at high imped-

ance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge”

or “grant sequence”.

ADDRESS/STATUS: During T1, these are the four most signiﬁcant address lines for memory op-

erations. During I/O operations these lines are LOW. During memory and I/O operations, status

information is available on these lines during T2, T3, TW, T4. S6 is always LOW. The status of

the interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3

are encoded as shown.

This information indicates which segment register is presently being used for data accessing.

These lines are held at high impedance to the last valid logic level during local bus “hold ac-

knowledge” or “grant sequence”.

CHARACTERISTICS

Alternate Data

Stack

Code or None

Data

A19/S6

A18/S5

A17/S4

A16/S3

35-38

BHE/S7

BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to

enable data onto the most signiﬁcant half of the data bus, pins D15-D8. Eight bit oriented devices

tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE

is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be trans-

ferred on the high portion of the bus. The S7 status information is available during T2, T3 and

T4. The signal is active LOW, and is held at high impedance to the last valid logic level during

interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”, it is LOW during

T1 for the ﬁrst interrupt acknowledge cycle.

BHE

CHARACTERISTICS

Whole Word

Upper Byte From/to Odd Address

Lower Byte From/to Even address

None

READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-

pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on

the 80C86 local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaran-

teed to remain HIGH in T2 until the 80C86 local bus has ﬂoated.

This line is held at a high impedance logic one state during “hold acknowledge” or “grand se-

quence”.

READY: is the acknowledgment from the addressed memory or I/O device that will complete the

data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Gener-

ator to form READY. This signal is active HIGH. The 80C86 READY input is not synchronized.

Correct operation is not guaranteed if the Setup and Hold Times are not met.

READY

3-144

80C86

Pin Description

(Continued)

The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is

the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).

NUMBER

SYMBOL

INTR

TYPE

DESCRIPTION

INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle

of each instruction to determine if the processor should enter into an interrupt acknowledge op-

eration. A subroutine is vectored to via an interrupt vector lookup table located in system mem-

ory. It can be internally masked by software resetting the interrupt enable bit.

lNTR is internally synchronized. This signal is active HIGH.

TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,

otherwise the processor waits in an “Idle” state. This input is synchronized internally during each

clock cycle on the leading edge of CLK.

NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A

subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is

not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the

end of the current instruction. This input is internally synchronized.

RESET: causes the processor to immediately terminate its present activity. The signal must tran-

sition LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution,

as described in the Instruction Set description, when RESET returns LOW. RESET is internally

synchronized.

CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a

33% duty cycle to provide optimized internal timing.

VCC: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for de-

coupling.

GND: Ground. Note: both must be connected. A 0.1µF capacitor between pins 1 and 20 is rec-

ommended for decoupling.

TEST

NMI

RESET

CLK

VCC

GND

1, 20

MN/MX

MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are

discussed in the following sections.

Minimum Mode System

The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = V

). Only the pin functions which are unique to

minimum mode are described; all other pin functions are as described below.

NUMBER

SYMBOL

M/IO

TYPE

DESCRIPTION

STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-

ory access from an I/O access. M/lO becomes valid in the T4 preceding a bus cycle and remains

valid until the ﬁnal T4 of the cycle (M = HIGH, I/O = LOW). M/lO is held to a high impedance logic

one during local bus “hold acknowledge”.

WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending

on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active

LOW, and is held to high impedance logic one during local bus “hold acknowledge”.

INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is

active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA is never

ﬂoated.

ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the

82C82/82C83 address latch. It is a HIGH pulse active during clock LOW of T1 of any bus cycle.

Note that ALE is never ﬂoated.

INTA

ALE

3-145

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