UL
®
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
TRIGGER
CLOCK SELECT
OSCILLATOR
EXTERNAL CLOCK
V
DD
(-V)
LS7210
(631) 271-0400 FAX (631) 271-0405
February 1998
PIN ASSIGNMENT - TOP VIEW
A3800
PROGRAMMABLE DIGITAL DELAY TIMER
FEATURES:
•
Programmable Delay from 6 ms to "Infinity"
• Can be Cascaded for Sequential Events or Extended Delay
• +4.75V to +15V Operation (Vss -V
DD
)
• On Chip Oscillator or External Clock time base
• High Noise Immunity
• LS7210 (DIP), LS7210-S (SOIC)-See Figure 1
DESCRIPTION:
The LS7210 is a monolithic MOS integrated circuit programmable
digital timer that can generate a delay in the range of 6ms to infinity.
The delay is programmed by 5 binary weighted input bits in combina-
tion with the time base provided. The chip can be operated in four
different modes: Delayed Operate, Delayed Release, Dual Delay
and One Shot. These modes are selected by the control inputs A
and B.
INPUT/OUTPUT DESCRIPTION:
OSCILLATOR Input
(Pin 5)
The frequency of the internal oscillator is set by an RC network con-
nected to the OSC input, as shown in Figure 2. The nominal os-
cillator frequency, f, at room temperature is given by f≈1/RC where R
values range from a minimum of 47KΩ to a maximum 3MΩ.
NOTE:
Oscillation accuracy from chip to chip for a fixed value of RC,
is + 10%. (Parts can supplied to tighter tolerances.)
B
1
A
2
3
14
13
12
V
SS
(+V)
OUT
WB0
WB1
WB2
WB3
WB4
LSI
LS7210
FIGURE 1
4
5
11
10
9
8
6
7
TABLE 1. WEIGHTING BITS ASSIGNMENTS
INPUTS
WB0
WB1
WB2
WB3
WB4
VALUE
1
2
4
8
16
Example:
For a weighting factor of 25, inputs WB4, WB3, and
EXTERNAL CLOCK Input
(Pin 6)
WB0 should be programmed to logic 0.
If the internal oscillator is not used, the chip can be driven by an ex-
ternal clock applied to this input.
MODE SELECT Inputs A, B
(Pins 2, 1)
The chip can be programmed to operate in four different modes
CLOCK SELECT Input
(Pin 4)
by applying the logic levels to inputs A and B as indicated in
The internal oscillator or the external clock is selected by the proper Table 2. The mode select inputs are clocked into the input latch-
logic level applied to this input. A logic 1 selects the external clock es with the negative edge of the time base clock. These inputs
and logic 0 selects the internal oscillator. (See Note 1)
should not be changed while a delay timing is in progress. (See
Note 1)
TRIGGER Input
(Pin 3)
TABLE 2. MODE SELECTION
A positive or a negative transition at the trigger input initiates a delay
in turning on or off the output. A negative transition always turns on
CONTROL
MODE
the output with or without delay depending on the selected mode. A
A
B
positive transition at the trigger input always turns off the output (with
1
1
Dual Delay
the exception of one-shot mode) with or without delay depending on
1
0
Delayed Release
the selected mode. The delay is a function of the time base fre-
0
1
Delayed Operate
quency and the weighting factor programmed at the weighting bit in-
0
0
One Shot
puts. The trigger input is clocked into the input latch with the neg-
ative edge of the selected time base clock. All timings begin after the
OUT Output
(Pin 13)
latch has been set up. (See Note 1)
The output is an open drain FET. To obtain proper switching of
the output between Logic 0 and 1 levels, an external pull down re-
sistor to V
DD
must be used. If the output is used only as a current
WEIGHTING FACTOR Inputs, WB0-WB4
(Pins 12-8)
source, no such pull down is needed. The output is logically in-
A delay from the trigger input to the output is programmed by ap- verted with respect to the trigger input.
plying 1's complement binary weighted numbers at these 5 inputs.
(See Note 1) The exact equation for the delay is:
V
SS
, V
DD
(Pins 14, 9)
Supply voltage positive, negative terminals.
(1 + 1, 023N)
f
= Oscillation Frequency
Delay
=
NOTE 1:
These inputs have internal pullup resistors.
f
N
= Weighting Factor
7210-041700-1
MODE DEFINITION TIMING DIAGRAM:
(See Figure 3)
DUAL DELAY MODE
Thls is the Default Mode when the inputs A and B are left un-
programmed. The function of the Dual Delay mode is to provide a
time delay on both the turn-on and turn-off of the output. Once turned
on, the output will remain on as long as the trigger input is Logic 0.
Once turned off, the output will remain off as long as the trigger input
is a logic 1.
DELAYED OPERATE MODE
This mode causes a retriggerable delay in turning the output on in re-
sponse to a negative edge at the trigger input. The output is turned
off without delay in response to a positive transition at the trigger in-
put.
DELAYED RELEASE MODE
This mode causes a retriggerable delay in turning off the output
whenever there is a positive transition at the trigger input. The out-
put is turned on without delay in response to a negative transition at
the trigger input.
ONE-SHOT MODE
In this mode, the chip functions like a retriggerable monostable
multi-vibrator. The output is turned on whenever there is a negative
transition at the trigger input. At the end of the programmed delay,
the output is turned off automatically. If there is a negative transition
at the trigger input before the delay is over, the delay is restarted.
A positive transition at the trigger input has no effect on the output
in this mode.
NOTE:
In One-Shot mode, the TRIGGER input must
be held at logic 1 during a power-up.
ABSOLUTE MAXIMUM RATINGS:
(All voltages referenced to V
DD
)
SYMBOL
VALUE
DC Supply Voltage
V
SS
+18
Voltage (Any Pin)
V
IN
0 to V
SS
+.3
Operating Temperature
T
A
-25 to +70
Storage Temperature
T
STG
-65 to +150
DC ELECTRICAL CHARACERISTICS:
(-25°C
≤T
A
≤+70°C
unless otherwise specified. All voltages referenced to V
DD
)
PARAMETER
Suppy Voltage
Supply Current
Trigger Input
Logic 1
Logic 0
All Other Inputs
Logic 1
Logic 0
Output
Source Current
for Vo = Vss - 1V
SYMBOL
V
SS
I
SS
MIN
+4.75
-
MAX
+15.0
3.0
UNIT
V
V
°C
°C
UNIT
V
mA
CONDITION
V
SS
= +15V, output off
V
TH
V
TL
V
SS
-1
0
V
SS
.2V
SS
V
V
-
-
V
IH
V
IL
.8V
SS
0
V
SS
.2V
SS
V
V
-
-
Io
Io
Io
+1.0
+2.8
+4.2
-
-
-
mA
mA
mA
V
SS
= + 5V
V
SS
= +10V
V
SS
= +15V
SWITCHING CHARACTERISTICS:
(See Figure 4)
PARAMETER
Oscillator Frequency
External Clock Frequency
External Clock, Positive Pulse Width
External Clock, Negative Pulse Width
A,B and Trigger Input Set-Up Time
Time-base Clock to Output Delay
(turn-on delay in Delayed Release mode
and turn-off delay in Delayed Operate mode)
Time-base Clock to Output Delay at the End of Time Out
Time-base Clock to Output Delay
(turn-on delay in One- Shot Mode)
SYMBOL
f
OSC
f
ext
t
H
t
L
t
S
MIN
-
DC
3
3
-
MAX
50
160
-
-
300
UNIT
KHz
KHz
µs
µs
ns
t
nd
t
od
t
sd
-
-
-
1
1.6
600
µs
µs
ns
7210-020298-2
+V
14
+V
C
5
R
OSC
TRIGGER
OUT (Dual Delay)
(C)
V
SS
OUT (Delayed Release)
FIGURE 2.
LS7210 OSCILLATOR CONNECTION
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
LS7210
OUT (Delayed Operate)
V
DD
7
(D)
OUT (One-Shot)
<
(A)
(B)
(E)
FIGURE 3. MODE DEFINITION TIMING DIAGRAM
A -
Turn-off delay in Dual Delay and Delayed Release mode.
B
- Turn-on delay in Dual Delay and Delayed Operate mode; one-shot period in One-Shot mode.
C
- Output remains on in Delayed Release and Dual Delay modes due to negative trigger
transition before the turn-off delay is over.
D
- Output remains off in Delayed Operate mode due to positive trigger transition before
the turn-on delay is over.
E
- One-Shot period extended by re-triggering.
Note:
∆
is the programmed delay.
t
L
TIME-BASE CLK
A
t
H
DELAYED RELEASE MODE
ONE-SHOT
MODE
B
TRIGGER
t
s
t
nd
PROGRAMMED
TURN-OFF
DELAY
t
od
t
sd
t
od
OUT
FIGURE 4. LS7210 TIMING DIAGRAM
N o t e 1 .
- A,B and Trigger inputs are clocked into the input latches with the negative edge of the time-base clock.
N o t e 2 .
- In all modes except One-Shot, the output changes with the positive transition of the time-base clock.
In One-Shot mode the output is turned on with the negative transition and turned off with the
positive transition of the time-base clock.
7210-020298-3
+V
FIGURE 5. LS7210 BLOCK DIAGRAM
+V
CLOCK
SELECT
EXT
CLOCK
4
6
8
9
10
+V
CLOCK
SELECT
LOGIC
11
12
PRESCALER
÷ 1023
(SEE NOTE)
WB4
WB3
WB2
WB1
WB0
+V
OSC 5
TIMER
OUTPUT
LATCH
13
OUT
+V
POR
GENERATOR
A
2
LATCH
2
+V
CONTROL LOGIC
B
1
LATCH
+V
TRIGGER
3
LATCH
V
SS
14
V
DD
7
+V
-V
NOTE:
÷ 1023 is standard. Any number from 1 to 1022 can be mask programmed.
FIGURE 6. ASYMMETRICAL FLASHER
1
B
2
3
A
V
SS
OUT
WB0
14
13
12
+V
OUT
+V
.005µF
TRIG
4
CS
LS7210
WB1
WB2
11
10
9
8
OUT
8.068 s
f
5
OSC
6
7
V
DD
EXT
CLK
68K
WB3
WB4
323ms
f = 3.17KHz
47K
NOTE:
7210-020298-4
Inputs A, B in Dual-Delay mode. For symmetical flasher tie Pins 8, 9, 10, 11 & 12 to fixed logic level.
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