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PE3341-53

Description
PLL/Frequency Synthesis Circuit
CategoryAnalog mixed-signal IC    The signal circuit   
File Size316KB,16 Pages
ManufacturerpSemi (peregrine semiconductor)
Websitehttp://www.psemi.com/
Environmental Compliance
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PE3341-53 Overview

PLL/Frequency Synthesis Circuit

PE3341-53 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerpSemi (peregrine semiconductor)
Reach Compliance Codeunknown
JESD-609 codee3
Humidity sensitivity level1
Terminal surfaceMatte Tin (Sn)
Base Number Matches1
Product Specification
PE3341
Product Description
The PE3341 is a high performance integer-N PLL with
embedded EEPROM capable of frequency synthesis up to
2700 MHz with a speed-grade option to 3000 MHz. The
EEPROM allows designers to permanently store control bits,
allowing easy configuration of self-starting synthesizers. The
superior phase noise performance of the PE3341 is ideal for
applications such as sonet, wireless base stations, fixed
wireless, and RF instrumentation systems.
The PE3341 features a ÷10/11 dual modulus prescaler,
counters, a phase comparator, and a charge pump as shown in
Figure 1. Counter values are programmable through a three-
wire serial interface.
The PE3341 UltraCMOS™ Phase Locked-Loop is
manufactured in Peregrine’s patented Ultra Thin Silicon
(UTSi®) CMOS process, offering excellent RF performance
with the economy and integration of conventional CMOS.
2700 MHz Integer-N PLL
with Field-Programmable EEPROM
Features
Field-programmable EEPROM for self-
starting applications
Standard 2700 MHz operation,
3000 MHz speed-grade option
÷10/11 dual modulus prescaler
Internal charge pump
Serial programmable
Low power — 20 mA at 3 V
Ultra-low phase noise
Available in 20-lead 4x4 mm QFN
package
Figure 1. Block Diagram
F
in
F
in
ENH
E_WR
Data
Clock
Serial
Interface
Mux
Enhancement
Register
(8-bit)
Primary
Register
(20-bit)
EE
Register
(20-bit)
Prescaler
÷10/11
M Counter
÷2 to ÷512
13
20
Secondary
Register
(20-bit)
PD_U
Phase
Detector
Charge
Pump
PD_D
CP
20
6
20
LD
2k
6
Cext
EELoad
Transfer
Logic
V
PP
S_WR
f
r
EESel
FSel
EEPROM
R Counter
÷1 to ÷64
Document No. 70-0053-05
www.psemi.com
©2005-8 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 17

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Description PLL/Frequency Synthesis Circuit PLL/Frequency Synthesis Circuit PLL/Frequency Synthesis Circuit
Is it Rohs certified? conform to conform to conform to
Maker pSemi (peregrine semiconductor) pSemi (peregrine semiconductor) pSemi (peregrine semiconductor)
Reach Compliance Code unknown unknown unknown
JESD-609 code e3 e3 e3
Humidity sensitivity level 1 1 1
Terminal surface Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn)
Base Number Matches 1 1 1
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